commit f65a252004d1f126bbfef820f87657b859adcccf Author: Jan Potocki Date: Sat Jun 2 16:31:19 2018 +0200 Initial commit diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..1f14cc2 --- /dev/null +++ b/LICENSE @@ -0,0 +1,9 @@ +/* + * ------------------------------------------------------------ + * "THE BEERWARE LICENSE" (Revision 42): + * wrote this code. As long as you retain this + * notice, you can do whatever you want with this stuff. If we + * meet someday, and you think this stuff is worth it, you can + * buy me a beer in return. + * ------------------------------------------------------------ +*/ diff --git a/README.md b/README.md new file mode 100644 index 0000000..3c76be9 --- /dev/null +++ b/README.md @@ -0,0 +1,5 @@ +# PWr - Układy cyfrowe i systemy wbudowane 2 P +Projekt z kursu UCiSW2 u doktora Sugiera - obsługa magnetometru HMC5883L i wykorzystanie go jako kompas wyświetlający pomiary na monitorze za pomocą wyjścia VGA. Implementacja projektu została wykonana na własnej płytce ZRtech Espier III z układem FPGA Xilinx Spartan-6 XC6SLX9 i sygnałem zegarowym o częstotliwości 48 MHz. + +Kontrolerem magnetometru jest moduł Magneto_Drv, komunikujący się z urządzeniem za pomocą modułu I2C_Master napisanego i udostępnionego przez doktora na stronie kursu. Za wyświetlanie kompasu na monitorze odpowiada moduł VGACompass generujący obraz o rozdzielczości 800x600 i częstotliwości odświeżania (około) 75 Hz. Moduł Display4x7S służy do wyświetlania pomiarów w osi Z (niewykorzystywanej przez kompas) na wyświetlaczu 7-segmentowym jako liczbę w systemie U16 - i jest klonem modułu o tej samej nazwie napisanego przez doktora dla laboratoryjnych płytek CPLD. Do ustawiania częstotliwości pomiarów według trybów z dokumentacji magnetometru służą przyciski S1-S3 (wciśnięcie - 1), nowe ustawienie obowiązuje od resetu układu (przycisk S4). Dioda D2 sygnalizuje nowy pomiar (DRDY), dioda D5 błąd w komunikacji I2C (NACK, zgaśnięcie - 1). +Film przedstawiający działanie projektu: www.youtube.com/watch?v=9VuPkd-sqCk \ No newline at end of file diff --git a/ucisw2_magnetometr/Display4x7S.spl b/ucisw2_magnetometr/Display4x7S.spl new file mode 100644 index 0000000..23cabe8 --- /dev/null +++ b/ucisw2_magnetometr/Display4x7S.spl @@ -0,0 +1,9 @@ +[Inputs] +Clk +=DI[15:0]= +=DP[3:0]= +=Blank[3:0]= +[Outputs] +=DS_EN[3:0]= +=DS[7:0]= +[BiDir] diff --git a/ucisw2_magnetometr/Display4x7S.sym b/ucisw2_magnetometr/Display4x7S.sym new file mode 100644 index 0000000..9427bf3 --- /dev/null +++ b/ucisw2_magnetometr/Display4x7S.sym @@ -0,0 +1,32 @@ + + + BLOCK + 2018-5-25T12:38:38 + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ucisw2_magnetometr/Display4x7S.vhd b/ucisw2_magnetometr/Display4x7S.vhd new file mode 100644 index 0000000..d47465f --- /dev/null +++ b/ucisw2_magnetometr/Display4x7S.vhd @@ -0,0 +1,119 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 21:30:49 01/03/2018 +-- Design Name: +-- Module Name: Display4x7S - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Display4x7S is + Port ( DI : in STD_LOGIC_VECTOR (15 downto 0); + DP : in STD_LOGIC_VECTOR (3 downto 0); + Blank : in STD_LOGIC_VECTOR (3 downto 0); + Clk : in STD_LOGIC; + DS_EN : out STD_LOGIC_VECTOR (3 downto 0); + DS : out STD_LOGIC_VECTOR (7 downto 0)); +end Display4x7S; + +architecture Behavioral of Display4x7S is + type state_type is (A, B, C, D); + signal state, next_state : state_type; + signal cycles : integer range 0 to 10000 := 0; + signal Bits : STD_LOGIC_VECTOR (3 downto 0); + signal Digit : STD_LOGIC_VECTOR (6 downto 0); + signal Point : STD_LOGIC; + +begin + process1 : process(Clk) + begin + if rising_edge(Clk) then + -- Clock frequency divider + -- 48 MHz -> 4800 Hz + -- (1200 Hz digit refresh rate) + if cycles = 10000 then + state <= next_state; + cycles <= 0; + else + cycles <= cycles + 1; + end if; + end if; + end process process1; + + process2 : process(state) + begin + next_state <= state; -- by default + + case state is + when A => + next_state <= B; + when B => + next_state <= C; + when C => + next_state <= D; + when D => + next_state <= A; + end case; + end process process2; + + Bits <= DI(3 downto 0) when state = A else + DI(7 downto 4) when state = B else + DI(11 downto 8) when state = C else + DI(15 downto 12) when state = D else + "0000"; + + Point <= DP(0) when state = A else + DP(1) when state = B else + DP(2) when state = C else + DP(3) when state = D else + '0'; + + with Bits select + Digit <= "0111111" when "0000", + "0000110" when "0001", + "1011011" when "0010", + "1001111" when "0011", + "1100110" when "0100", + "1101101" when "0101", + "1111101" when "0110", + "0000111" when "0111", + "1111111" when "1000", + "1101111" when "1001", + "1011111" when "1010", + "1111100" when "1011", + "0111001" when "1100", + "1011110" when "1101", + "1111001" when "1110", + "1110001" when "1111", + "0000000" when others; + + DS_EN <= "1110" when state = A and Blank(0) = '0' else + "1101" when state = B and Blank(1) = '0' else + "1011" when state = C and Blank(2) = '0' else + "0111" when state = D and Blank(3) = '0' else + "1111"; + + DS <= Point & Digit; +end Behavioral; diff --git a/ucisw2_magnetometr/ESPIER_III.ucf b/ucisw2_magnetometr/ESPIER_III.ucf new file mode 100644 index 0000000..40283a3 --- /dev/null +++ b/ucisw2_magnetometr/ESPIER_III.ucf @@ -0,0 +1,117 @@ +## ESPIER III V105 Spartan-6 board constraint file v1.1 +## J. Potocki 2018 + +# Clock +NET "CLK" LOC = P56 | PERIOD = 20.83ns HIGH 50%; + +# Keys +NET "Rate<0>" LOC = P15; +NET "Rate<1>" LOC = P21; +NET "Rate<2>" LOC = P17; +NET "Reset" LOC = P16; + +# LEDs +NET "DRLED" LOC = P95 | SLEW = "SLOW"; +#NET "LED<1>" LOC = P94 | SLEW = "SLOW"; +#NET "LED<2>" LOC = P98 | SLEW = "SLOW"; +NET "NACK" LOC = P97 | SLEW = "SLOW"; + +# DISPL. 7-SEG +NET "DS_EN<0>" LOC = P75 | SLEW = "SLOW"; +NET "DS_EN<1>" LOC = P67 | SLEW = "SLOW"; +NET "DS_EN<2>" LOC = P74 | SLEW = "SLOW"; +NET "DS_EN<3>" LOC = P66 | SLEW = "SLOW"; +NET "DS<0>" LOC = P80; # Seg. A +NET "DS<1>" LOC = P79; # Seg. B +NET "DS<2>" LOC = P83; # Seg. C +NET "DS<3>" LOC = P82; # Seg. D +NET "DS<4>" LOC = P81; # Seg. E +NET "DS<5>" LOC = P78; # Seg. F +NET "DS<6>" LOC = P84; # Seg. G +NET "DS<7>" LOC = P85; # Seg. DP + +# PS/2 +#NET "PS2_CLK" LOC = P24 | SLEW = "SLOW"; +#NET "PS2_DATA" LOC = P23 | SLEW = "SLOW"; + +# IrDA +#NET "IRDA" LOC = P62 | SLEW = "SLOW"; + +# RS-232 PL-2303 (clone) +#NET "RS_TXD" LOC = P12 | SLEW = "SLOW"; +#NET "RS_RXD" LOC = P14 | SLEW = "SLOW"; + +# ADC +#NET "ADCSN" LOC = P61 | SLEW = "SLOW"; +#NET "ADDAT" LOC = P59 | SLEW = "SLOW"; +#NET "ADCLK" LOC = P55 | SLEW = "SLOW"; + +# SPI FLASH +#NET "FLASH_CLK" LOC = P88 | SLEW = "SLOW"; +#NET "FLASH_CS" LOC = P93 | SLEW = "SLOW"; +#NET "FLASH_DI" LOC = P87 | SLEW = "SLOW"; +#NET "FLASH_DO" LOC = P92 | SLEW = "SLOW"; + +# Buzzer +#NET "BP1" LOC = P11 | SLEW = "SLOW"; + +# VGA +NET "V_R<0>" LOC = P46 | SLEW = FAST; +NET "V_R<1>" LOC = P47 | SLEW = FAST; +NET "V_R<2>" LOC = P48 | SLEW = FAST; +NET "V_R<3>" LOC = P50 | SLEW = FAST; +NET "V_R<4>" LOC = P51 | SLEW = FAST; +NET "V_G<0>" LOC = P35 | SLEW = FAST; +NET "V_G<1>" LOC = P40 | SLEW = FAST; +NET "V_G<2>" LOC = P41 | SLEW = FAST; +NET "V_G<3>" LOC = P43 | SLEW = FAST; +NET "V_G<4>" LOC = P44 | SLEW = FAST; +NET "V_G<5>" LOC = P45 | SLEW = FAST; +NET "V_B<0>" LOC = P29 | SLEW = FAST; +NET "V_B<1>" LOC = P30 | SLEW = FAST; +NET "V_B<2>" LOC = P32 | SLEW = FAST; +NET "V_B<3>" LOC = P33 | SLEW = FAST; +NET "V_B<4>" LOC = P34 | SLEW = FAST; +NET "V_SYNC" LOC = P27 | SLEW = FAST; +NET "H_SYNC" LOC = P26 | SLEW = FAST; + +# SDRAM +#NET "SDRAM_A<0>" LOC = P7; +#NET "SDRAM_A<1>" LOC = P8; +#NET "SDRAM_A<2>" LOC = P9; +#NET "SDRAM_A<3>" LOC = P10; +#NET "SDRAM_A<4>" LOC = P143; +#NET "SDRAM_A<5>" LOC = P142; +#NET "SDRAM_A<6>" LOC = P141; +#NET "SDRAM_A<7>" LOC = P140; +#NET "SDRAM_A<8>" LOC = P139; +#NET "SDRAM_A<9>" LOC = P138; +#NET "SDRAM_A<10>" LOC = P6; +#NET "SDRAM_A<11>" LOC = P137; +#NET "SDRAM_A<12>" LOC = P134; +#NET "SDRAM_BA<1>" LOC = P5; +#NET "SDRAM_BA<0>" LOC = P2; +#NET "SDRAM_CKE" LOC = P133; +#NET "SDRAM_CLK" LOC = P132; +#NET "SDRAM_CS_N" LOC = P1; +#NET "SDRAM_DQMH" LOC = P131; +#NET "SDRAM_DQML" LOC = P114; +#NET "SDRAM_WE_N" LOC = P115; +#NET "SDRAM_CAS_N" LOC = P116; +#NET "SDRAM_RAS_N" LOC = P117; +#NET "SDRAM_DQ<0>" LOC = P100; +#NET "SDRAM_DQ<1>" LOC = P99; +#NET "SDRAM_DQ<2>" LOC = P102; +#NET "SDRAM_DQ<3>" LOC = P101; +#NET "SDRAM_DQ<4>" LOC = P104; +#NET "SDRAM_DQ<5>" LOC = P105; +#NET "SDRAM_DQ<6>" LOC = P111; +#NET "SDRAM_DQ<7>" LOC = P112; +#NET "SDRAM_DQ<8>" LOC = P127; +#NET "SDRAM_DQ<9>" LOC = P126; +#NET "SDRAM_DQ<10>" LOC = P124; +#NET "SDRAM_DQ<11>" LOC = P123; +#NET "SDRAM_DQ<12>" LOC = P121; +#NET "SDRAM_DQ<13>" LOC = P120; +#NET "SDRAM_DQ<14>" LOC = P119; +#NET "SDRAM_DQ<15>" LOC = P118; \ No newline at end of file diff --git a/ucisw2_magnetometr/I2C_Master.sym b/ucisw2_magnetometr/I2C_Master.sym new file mode 100644 index 0000000..acae0b2 --- /dev/null +++ b/ucisw2_magnetometr/I2C_Master.sym @@ -0,0 +1,58 @@ + + + BLOCK + 2015-11-24T12:12:48 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ucisw2_magnetometr/I2C_Master.vhd b/ucisw2_magnetometr/I2C_Master.vhd new file mode 100644 index 0000000..0f0b641 --- /dev/null +++ b/ucisw2_magnetometr/I2C_Master.vhd @@ -0,0 +1,2348 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version: P.20131013 +-- \ \ Application: netgen +-- / / Filename: i2c_master.vhd +-- /___/ /\ Timestamp: Wed Mar 02 21:13:40 2016 +-- \ \ / \ +-- \___\/\___\ +-- +-- Command : -ofmt vhdl i2c_master.ngc +-- Device : xc3s500e-4-fg320 +-- Input file : i2c_master.ngc +-- Output file : i2c_master.vhd +-- # of Entities : 1 +-- Design Name : I2C_Master +-- Xilinx : C:\Xilinx\14.7\ISE_DS\ISE\ +-- +-- Purpose: +-- This VHDL netlist is a verification model and uses simulation +-- primitives which may not represent the true implementation of the +-- device, however the netlist is functionally correct and should not +-- be modified. +-- +-- Reference: +-- Command Line Tools User Guide, Chapter 23 +-- Synthesis and Simulation Design Guide, Chapter 6 +-- +-------------------------------------------------------------------------------- + +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +library UNISIM; +use UNISIM.VCOMPONENTS.ALL; + +entity I2C_Master is + port ( + SDA : inout STD_LOGIC; + SCL : inout STD_LOGIC; + Clk : in STD_LOGIC := 'X'; + NACK : out STD_LOGIC; + FIFO_Pop : in STD_LOGIC := 'X'; + Reset : in STD_LOGIC := 'X'; + Go : in STD_LOGIC := 'X'; + Busy : out STD_LOGIC; + FIFO_Empty : out STD_LOGIC; + FIFO_Push : in STD_LOGIC := 'X'; + FIFO_Full : out STD_LOGIC; + FIFO_DO : out STD_LOGIC_VECTOR ( 7 downto 0 ); + Address : in STD_LOGIC_VECTOR ( 7 downto 0 ); + FIFO_DI : in STD_LOGIC_VECTOR ( 7 downto 0 ); + ReadCnt : in STD_LOGIC_VECTOR ( 3 downto 0 ) + ); +end I2C_Master; + +architecture STRUCTURE of I2C_Master is + signal Mcount_cntBytes : STD_LOGIC; + signal Mcount_cntBytes1 : STD_LOGIC; + signal Mcount_cntBytes2 : STD_LOGIC; + signal Mcount_cntBytes3 : STD_LOGIC; + signal Mcount_cntSCL_cy_1_rt_43 : STD_LOGIC; + signal Mcount_cntSCL_cy_2_rt_45 : STD_LOGIC; + signal Mcount_cntSCL_cy_3_rt_47 : STD_LOGIC; + signal Mcount_cntSCL_cy_4_rt_49 : STD_LOGIC; + signal Mcount_cntSCL_cy_5_rt_51 : STD_LOGIC; + signal Mcount_cntSCL_cy_6_rt_53 : STD_LOGIC; + signal Mcount_cntSCL_xor_7_rt_55 : STD_LOGIC; + signal N0 : STD_LOGIC; + signal N01 : STD_LOGIC; + signal N1 : STD_LOGIC; + signal N107 : STD_LOGIC; + signal N109 : STD_LOGIC; + signal N111 : STD_LOGIC; + signal N1111 : STD_LOGIC; + signal N112 : STD_LOGIC; + signal N113 : STD_LOGIC; + signal N114 : STD_LOGIC; + signal N115 : STD_LOGIC; + signal N116 : STD_LOGIC; + signal N117 : STD_LOGIC; + signal N118 : STD_LOGIC; + signal N12 : STD_LOGIC; + signal N14 : STD_LOGIC; + signal N15 : STD_LOGIC; + signal N55 : STD_LOGIC; + signal N57 : STD_LOGIC; + signal N59 : STD_LOGIC; + signal N61 : STD_LOGIC; + signal N62 : STD_LOGIC; + signal N64 : STD_LOGIC; + signal N65 : STD_LOGIC; + signal N69 : STD_LOGIC; + signal N71 : STD_LOGIC; + signal N73 : STD_LOGIC; + signal N75 : STD_LOGIC; + signal N77 : STD_LOGIC; + signal N79 : STD_LOGIC; + signal N80 : STD_LOGIC; + signal N82 : STD_LOGIC; + signal N84 : STD_LOGIC; + signal N85 : STD_LOGIC; + signal N87 : STD_LOGIC; + signal N90 : STD_LOGIC; + signal N92 : STD_LOGIC; + signal NACK_and0000 : STD_LOGIC; + signal NACK_and00007_95 : STD_LOGIC; + signal RdNotWr_96 : STD_LOGIC; + signal RdNotWr_and0000 : STD_LOGIC; + signal Result_0_1 : STD_LOGIC; + signal Result_1_1 : STD_LOGIC; + signal Result_2_1 : STD_LOGIC; + signal Result_3_1 : STD_LOGIC; + signal SCLout_116 : STD_LOGIC; + signal SCLout_mux000017_117 : STD_LOGIC; + signal SCLout_mux000021_118 : STD_LOGIC; + signal SCLout_mux000061_119 : STD_LOGIC; + signal SCLout_mux000063_120 : STD_LOGIC; + signal SCLout_mux000072 : STD_LOGIC; + signal SCLout_mux00008_122 : STD_LOGIC; + signal SDAin : STD_LOGIC; + signal SDAout_125 : STD_LOGIC; + signal SDAout_mux0003107_126 : STD_LOGIC; + signal SDAout_mux0003112_127 : STD_LOGIC; + signal SDAout_mux0003139_128 : STD_LOGIC; + signal SDAout_mux0003157_129 : STD_LOGIC; + signal SDAout_mux000316_130 : STD_LOGIC; + signal SDAout_mux0003180_131 : STD_LOGIC; + signal SDAout_mux0003204 : STD_LOGIC; + signal SDAout_mux000325_133 : STD_LOGIC; + signal SDAout_mux000337_134 : STD_LOGIC; + signal SDAout_mux0003412_135 : STD_LOGIC; + signal SDAout_mux0003425_136 : STD_LOGIC; + signal SDAout_mux0003431_137 : STD_LOGIC; + signal SDAout_mux000358_138 : STD_LOGIC; + signal SDAout_mux00038_139 : STD_LOGIC; + signal SDAout_mux000388_140 : STD_LOGIC; + signal SDAout_mux000393_141 : STD_LOGIC; + signal cntBits_or0000 : STD_LOGIC; + signal cntBytes_not0001_151 : STD_LOGIC; + signal cntSCL_or0000 : STD_LOGIC; + signal i_FIFO_DoPop_161 : STD_LOGIC; + signal i_FIFO_DoPush : STD_LOGIC; + signal i_FIFO_DoPush0_163 : STD_LOGIC; + signal i_FIFO_DoPush13_164 : STD_LOGIC; + signal i_FIFO_Result_0_1 : STD_LOGIC; + signal i_FIFO_Result_1_1_168 : STD_LOGIC; + signal i_FIFO_Result_2_1_170 : STD_LOGIC; + signal i_FIFO_Result_3_1 : STD_LOGIC; + signal NlwRenamedSig_OI_i_FIFO_iEmpty : STD_LOGIC; + signal i_FIFO_iEmpty_and0000 : STD_LOGIC; + signal i_FIFO_iEmpty_and000058_183 : STD_LOGIC; + signal i_FIFO_iEmpty_and000067_184 : STD_LOGIC; + signal i_FIFO_iEmpty_or0000 : STD_LOGIC; + signal NlwRenamedSig_OI_i_FIFO_iFull : STD_LOGIC; + signal i_FIFO_iFull_and0000 : STD_LOGIC; + signal i_FIFO_iFull_and000048_188 : STD_LOGIC; + signal i_FIFO_iFull_and000071_189 : STD_LOGIC; + signal i_FIFO_iFull_and000076_190 : STD_LOGIC; + signal i_FIFO_iFull_or0000 : STD_LOGIC; + signal sclEnd : STD_LOGIC; + signal sregIn_and0000 : STD_LOGIC; + signal sregOut_mux0000_1_1_212 : STD_LOGIC; + signal sregOut_mux0000_1_2_213 : STD_LOGIC; + signal sregOut_mux0000_2_1_215 : STD_LOGIC; + signal sregOut_mux0000_2_2_216 : STD_LOGIC; + signal sregOut_mux0000_3_1_218 : STD_LOGIC; + signal sregOut_mux0000_3_2_219 : STD_LOGIC; + signal sregOut_mux0000_4_1_221 : STD_LOGIC; + signal sregOut_mux0000_4_2_222 : STD_LOGIC; + signal sregOut_mux0000_5_1_224 : STD_LOGIC; + signal sregOut_mux0000_5_2_225 : STD_LOGIC; + signal sregOut_mux0000_6_1_227 : STD_LOGIC; + signal sregOut_mux0000_6_2_228 : STD_LOGIC; + signal sregOut_mux0000_7_1_230 : STD_LOGIC; + signal sregOut_mux0000_7_2_231 : STD_LOGIC; + signal sregOut_not0001_232 : STD_LOGIC; + signal state_FSM_FFd1_233 : STD_LOGIC; + signal state_FSM_FFd1_In_234 : STD_LOGIC; + signal state_FSM_FFd2_235 : STD_LOGIC; + signal state_FSM_FFd2_In12_236 : STD_LOGIC; + signal state_FSM_FFd2_In2_237 : STD_LOGIC; + signal state_FSM_FFd2_In26_238 : STD_LOGIC; + signal state_FSM_FFd3_239 : STD_LOGIC; + signal state_FSM_FFd3_In_240 : STD_LOGIC; + signal state_FSM_FFd4_241 : STD_LOGIC; + signal state_FSM_FFd4_In : STD_LOGIC; + signal state_FSM_FFd5_243 : STD_LOGIC; + signal state_FSM_FFd5_In1_244 : STD_LOGIC; + signal state_FSM_FFd6_245 : STD_LOGIC; + signal NLW_IOB2_O_UNCONNECTED : STD_LOGIC; + signal NLW_i_FIFO_Mram_RAM8_SPO_UNCONNECTED : STD_LOGIC; + signal NLW_i_FIFO_Mram_RAM7_SPO_UNCONNECTED : STD_LOGIC; + signal NLW_i_FIFO_Mram_RAM6_SPO_UNCONNECTED : STD_LOGIC; + signal NLW_i_FIFO_Mram_RAM5_SPO_UNCONNECTED : STD_LOGIC; + signal NLW_i_FIFO_Mram_RAM4_SPO_UNCONNECTED : STD_LOGIC; + signal NLW_i_FIFO_Mram_RAM3_SPO_UNCONNECTED : STD_LOGIC; + signal NLW_i_FIFO_Mram_RAM2_SPO_UNCONNECTED : STD_LOGIC; + signal NLW_i_FIFO_Mram_RAM1_SPO_UNCONNECTED : STD_LOGIC; + signal DI : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal NlwRenamedSig_OI_FIFO_DO : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal Mcount_cntSCL_cy : STD_LOGIC_VECTOR ( 6 downto 0 ); + signal Mcount_cntSCL_lut : STD_LOGIC_VECTOR ( 0 downto 0 ); + signal Result : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal cntBits : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal cntBytes : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal cntSCL : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal i_FIFO_Result : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal i_FIFO_addrRd : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal i_FIFO_addrWr : STD_LOGIC_VECTOR ( 3 downto 0 ); + signal sregIn : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal sregOut : STD_LOGIC_VECTOR ( 7 downto 0 ); + signal sregOut_mux0000 : STD_LOGIC_VECTOR ( 7 downto 0 ); +begin + FIFO_Empty <= NlwRenamedSig_OI_i_FIFO_iEmpty; + FIFO_Full <= NlwRenamedSig_OI_i_FIFO_iFull; + FIFO_DO(7) <= NlwRenamedSig_OI_FIFO_DO(7); + FIFO_DO(6) <= NlwRenamedSig_OI_FIFO_DO(6); + FIFO_DO(5) <= NlwRenamedSig_OI_FIFO_DO(5); + FIFO_DO(4) <= NlwRenamedSig_OI_FIFO_DO(4); + FIFO_DO(3) <= NlwRenamedSig_OI_FIFO_DO(3); + FIFO_DO(2) <= NlwRenamedSig_OI_FIFO_DO(2); + FIFO_DO(1) <= NlwRenamedSig_OI_FIFO_DO(1); + FIFO_DO(0) <= NlwRenamedSig_OI_FIFO_DO(0); + XST_GND : GND + port map ( + G => N0 + ); + XST_VCC : VCC + port map ( + P => N1 + ); + RdNotWr : FDE + port map ( + C => Clk, + CE => RdNotWr_and0000, + D => Address(0), + Q => RdNotWr_96 + ); + sregOut_0 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregOut_not0001_232, + D => sregOut_mux0000(0), + Q => sregOut(0) + ); + sregOut_1 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregOut_not0001_232, + D => sregOut_mux0000(1), + Q => sregOut(1) + ); + sregOut_2 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregOut_not0001_232, + D => sregOut_mux0000(2), + Q => sregOut(2) + ); + sregOut_3 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregOut_not0001_232, + D => sregOut_mux0000(3), + Q => sregOut(3) + ); + sregOut_4 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregOut_not0001_232, + D => sregOut_mux0000(4), + Q => sregOut(4) + ); + sregOut_5 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregOut_not0001_232, + D => sregOut_mux0000(5), + Q => sregOut(5) + ); + sregOut_6 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregOut_not0001_232, + D => sregOut_mux0000(6), + Q => sregOut(6) + ); + sregOut_7 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregOut_not0001_232, + D => sregOut_mux0000(7), + Q => sregOut(7) + ); + NACK_12 : FDRE + port map ( + C => Clk, + CE => NACK_and0000, + D => N1, + R => state_FSM_FFd6_245, + Q => NACK + ); + sregIn_0 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregIn_and0000, + D => SDAin, + Q => sregIn(0) + ); + sregIn_1 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregIn_and0000, + D => sregIn(0), + Q => sregIn(1) + ); + sregIn_2 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregIn_and0000, + D => sregIn(1), + Q => sregIn(2) + ); + sregIn_3 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregIn_and0000, + D => sregIn(2), + Q => sregIn(3) + ); + sregIn_4 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregIn_and0000, + D => sregIn(3), + Q => sregIn(4) + ); + sregIn_5 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregIn_and0000, + D => sregIn(4), + Q => sregIn(5) + ); + sregIn_6 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregIn_and0000, + D => sregIn(5), + Q => sregIn(6) + ); + sregIn_7 : FDE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sregIn_and0000, + D => sregIn(6), + Q => sregIn(7) + ); + cntBits_0 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sclEnd, + D => Result(0), + R => cntBits_or0000, + Q => cntBits(0) + ); + cntBits_1 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sclEnd, + D => Result(1), + R => cntBits_or0000, + Q => cntBits(1) + ); + cntBits_2 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sclEnd, + D => Result(2), + R => cntBits_or0000, + Q => cntBits(2) + ); + cntBits_3 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sclEnd, + D => Result(3), + R => cntBits_or0000, + Q => cntBits(3) + ); + cntSCL_0 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => Result_0_1, + R => cntSCL_or0000, + Q => cntSCL(0) + ); + cntSCL_1 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => Result_1_1, + R => cntSCL_or0000, + Q => cntSCL(1) + ); + cntSCL_2 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => Result_2_1, + R => cntSCL_or0000, + Q => cntSCL(2) + ); + cntSCL_3 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => Result_3_1, + R => cntSCL_or0000, + Q => cntSCL(3) + ); + cntSCL_4 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => Result(4), + R => cntSCL_or0000, + Q => cntSCL(4) + ); + cntSCL_5 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => Result(5), + R => cntSCL_or0000, + Q => cntSCL(5) + ); + cntSCL_6 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => Result(6), + R => cntSCL_or0000, + Q => cntSCL(6) + ); + cntSCL_7 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => Result(7), + R => cntSCL_or0000, + Q => cntSCL(7) + ); + cntBytes_0 : FDE + port map ( + C => Clk, + CE => cntBytes_not0001_151, + D => Mcount_cntBytes, + Q => cntBytes(0) + ); + cntBytes_1 : FDE + port map ( + C => Clk, + CE => cntBytes_not0001_151, + D => Mcount_cntBytes1, + Q => cntBytes(1) + ); + cntBytes_2 : FDE + port map ( + C => Clk, + CE => cntBytes_not0001_151, + D => Mcount_cntBytes2, + Q => cntBytes(2) + ); + cntBytes_3 : FDE + port map ( + C => Clk, + CE => cntBytes_not0001_151, + D => Mcount_cntBytes3, + Q => cntBytes(3) + ); + Mcount_cntSCL_cy_0_Q : MUXCY + port map ( + CI => N0, + DI => N1, + S => Mcount_cntSCL_lut(0), + O => Mcount_cntSCL_cy(0) + ); + Mcount_cntSCL_xor_0_Q : XORCY + port map ( + CI => N0, + LI => Mcount_cntSCL_lut(0), + O => Result_0_1 + ); + Mcount_cntSCL_cy_1_Q : MUXCY + port map ( + CI => Mcount_cntSCL_cy(0), + DI => N0, + S => Mcount_cntSCL_cy_1_rt_43, + O => Mcount_cntSCL_cy(1) + ); + Mcount_cntSCL_xor_1_Q : XORCY + port map ( + CI => Mcount_cntSCL_cy(0), + LI => Mcount_cntSCL_cy_1_rt_43, + O => Result_1_1 + ); + Mcount_cntSCL_cy_2_Q : MUXCY + port map ( + CI => Mcount_cntSCL_cy(1), + DI => N0, + S => Mcount_cntSCL_cy_2_rt_45, + O => Mcount_cntSCL_cy(2) + ); + Mcount_cntSCL_xor_2_Q : XORCY + port map ( + CI => Mcount_cntSCL_cy(1), + LI => Mcount_cntSCL_cy_2_rt_45, + O => Result_2_1 + ); + Mcount_cntSCL_cy_3_Q : MUXCY + port map ( + CI => Mcount_cntSCL_cy(2), + DI => N0, + S => Mcount_cntSCL_cy_3_rt_47, + O => Mcount_cntSCL_cy(3) + ); + Mcount_cntSCL_xor_3_Q : XORCY + port map ( + CI => Mcount_cntSCL_cy(2), + LI => Mcount_cntSCL_cy_3_rt_47, + O => Result_3_1 + ); + Mcount_cntSCL_cy_4_Q : MUXCY + port map ( + CI => Mcount_cntSCL_cy(3), + DI => N0, + S => Mcount_cntSCL_cy_4_rt_49, + O => Mcount_cntSCL_cy(4) + ); + Mcount_cntSCL_xor_4_Q : XORCY + port map ( + CI => Mcount_cntSCL_cy(3), + LI => Mcount_cntSCL_cy_4_rt_49, + O => Result(4) + ); + Mcount_cntSCL_cy_5_Q : MUXCY + port map ( + CI => Mcount_cntSCL_cy(4), + DI => N0, + S => Mcount_cntSCL_cy_5_rt_51, + O => Mcount_cntSCL_cy(5) + ); + Mcount_cntSCL_xor_5_Q : XORCY + port map ( + CI => Mcount_cntSCL_cy(4), + LI => Mcount_cntSCL_cy_5_rt_51, + O => Result(5) + ); + Mcount_cntSCL_cy_6_Q : MUXCY + port map ( + CI => Mcount_cntSCL_cy(5), + DI => N0, + S => Mcount_cntSCL_cy_6_rt_53, + O => Mcount_cntSCL_cy(6) + ); + Mcount_cntSCL_xor_6_Q : XORCY + port map ( + CI => Mcount_cntSCL_cy(5), + LI => Mcount_cntSCL_cy_6_rt_53, + O => Result(6) + ); + Mcount_cntSCL_xor_7_Q : XORCY + port map ( + CI => Mcount_cntSCL_cy(6), + LI => Mcount_cntSCL_xor_7_rt_55, + O => Result(7) + ); + IOB1 : IOBUF + generic map( + CAPACITANCE => "DONT_CARE", + DRIVE => 12, + IBUF_DELAY_VALUE => "0", + IBUF_LOW_PWR => TRUE, + IFD_DELAY_VALUE => "AUTO", + IOSTANDARD => "DEFAULT", + SLEW => "20" + ) + port map ( + I => N0, + T => SDAout_125, + O => SDAin, + IO => SDA + ); + IOB2 : IOBUF + generic map( + CAPACITANCE => "DONT_CARE", + DRIVE => 12, + IBUF_DELAY_VALUE => "0", + IBUF_LOW_PWR => TRUE, + IFD_DELAY_VALUE => "AUTO", + IOSTANDARD => "DEFAULT", + SLEW => "20" + ) + port map ( + I => N0, + T => SCLout_116, + O => NLW_IOB2_O_UNCONNECTED, + IO => SCL + ); + state_FSM_FFd3 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => state_FSM_FFd3_In_240, + R => Reset, + Q => state_FSM_FFd3_239 + ); + state_FSM_FFd1 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => state_FSM_FFd1_In_234, + R => Reset, + Q => state_FSM_FFd1_233 + ); + state_FSM_FFd6 : FDS + generic map( + INIT => '1' + ) + port map ( + C => Clk, + D => N0, + S => Reset, + Q => state_FSM_FFd6_245 + ); + state_FSM_FFd4 : FDR + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => state_FSM_FFd4_In, + R => Reset, + Q => state_FSM_FFd4_241 + ); + i_FIFO_addrWr_3 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_DoPush, + D => i_FIFO_Result_3_1, + R => Reset, + Q => i_FIFO_addrWr(3) + ); + i_FIFO_addrWr_2 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_DoPush, + D => i_FIFO_Result_2_1_170, + R => Reset, + Q => i_FIFO_addrWr(2) + ); + i_FIFO_addrWr_1 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_DoPush, + D => i_FIFO_Result_1_1_168, + R => Reset, + Q => i_FIFO_addrWr(1) + ); + i_FIFO_addrWr_0 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_DoPush, + D => i_FIFO_Result_0_1, + R => Reset, + Q => i_FIFO_addrWr(0) + ); + i_FIFO_addrRd_3 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_DoPop_161, + D => i_FIFO_Result(3), + R => Reset, + Q => i_FIFO_addrRd(3) + ); + i_FIFO_addrRd_2 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_DoPop_161, + D => i_FIFO_Result(2), + R => Reset, + Q => i_FIFO_addrRd(2) + ); + i_FIFO_addrRd_1 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_DoPop_161, + D => i_FIFO_Result(1), + R => Reset, + Q => i_FIFO_addrRd(1) + ); + i_FIFO_addrRd_0 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_DoPop_161, + D => i_FIFO_Result(0), + R => Reset, + Q => i_FIFO_addrRd(0) + ); + i_FIFO_Mram_RAM8 : RAM16X1D + port map ( + A0 => i_FIFO_addrWr(0), + A1 => i_FIFO_addrWr(1), + A2 => i_FIFO_addrWr(2), + A3 => i_FIFO_addrWr(3), + D => DI(7), + DPRA0 => i_FIFO_addrRd(0), + DPRA1 => i_FIFO_addrRd(1), + DPRA2 => i_FIFO_addrRd(2), + DPRA3 => i_FIFO_addrRd(3), + WCLK => Clk, + WE => i_FIFO_DoPush, + SPO => NLW_i_FIFO_Mram_RAM8_SPO_UNCONNECTED, + DPO => NlwRenamedSig_OI_FIFO_DO(7) + ); + i_FIFO_Mram_RAM7 : RAM16X1D + port map ( + A0 => i_FIFO_addrWr(0), + A1 => i_FIFO_addrWr(1), + A2 => i_FIFO_addrWr(2), + A3 => i_FIFO_addrWr(3), + D => DI(6), + DPRA0 => i_FIFO_addrRd(0), + DPRA1 => i_FIFO_addrRd(1), + DPRA2 => i_FIFO_addrRd(2), + DPRA3 => i_FIFO_addrRd(3), + WCLK => Clk, + WE => i_FIFO_DoPush, + SPO => NLW_i_FIFO_Mram_RAM7_SPO_UNCONNECTED, + DPO => NlwRenamedSig_OI_FIFO_DO(6) + ); + i_FIFO_Mram_RAM6 : RAM16X1D + port map ( + A0 => i_FIFO_addrWr(0), + A1 => i_FIFO_addrWr(1), + A2 => i_FIFO_addrWr(2), + A3 => i_FIFO_addrWr(3), + D => DI(5), + DPRA0 => i_FIFO_addrRd(0), + DPRA1 => i_FIFO_addrRd(1), + DPRA2 => i_FIFO_addrRd(2), + DPRA3 => i_FIFO_addrRd(3), + WCLK => Clk, + WE => i_FIFO_DoPush, + SPO => NLW_i_FIFO_Mram_RAM6_SPO_UNCONNECTED, + DPO => NlwRenamedSig_OI_FIFO_DO(5) + ); + i_FIFO_Mram_RAM5 : RAM16X1D + port map ( + A0 => i_FIFO_addrWr(0), + A1 => i_FIFO_addrWr(1), + A2 => i_FIFO_addrWr(2), + A3 => i_FIFO_addrWr(3), + D => DI(4), + DPRA0 => i_FIFO_addrRd(0), + DPRA1 => i_FIFO_addrRd(1), + DPRA2 => i_FIFO_addrRd(2), + DPRA3 => i_FIFO_addrRd(3), + WCLK => Clk, + WE => i_FIFO_DoPush, + SPO => NLW_i_FIFO_Mram_RAM5_SPO_UNCONNECTED, + DPO => NlwRenamedSig_OI_FIFO_DO(4) + ); + i_FIFO_Mram_RAM4 : RAM16X1D + port map ( + A0 => i_FIFO_addrWr(0), + A1 => i_FIFO_addrWr(1), + A2 => i_FIFO_addrWr(2), + A3 => i_FIFO_addrWr(3), + D => DI(3), + DPRA0 => i_FIFO_addrRd(0), + DPRA1 => i_FIFO_addrRd(1), + DPRA2 => i_FIFO_addrRd(2), + DPRA3 => i_FIFO_addrRd(3), + WCLK => Clk, + WE => i_FIFO_DoPush, + SPO => NLW_i_FIFO_Mram_RAM4_SPO_UNCONNECTED, + DPO => NlwRenamedSig_OI_FIFO_DO(3) + ); + i_FIFO_Mram_RAM3 : RAM16X1D + port map ( + A0 => i_FIFO_addrWr(0), + A1 => i_FIFO_addrWr(1), + A2 => i_FIFO_addrWr(2), + A3 => i_FIFO_addrWr(3), + D => DI(2), + DPRA0 => i_FIFO_addrRd(0), + DPRA1 => i_FIFO_addrRd(1), + DPRA2 => i_FIFO_addrRd(2), + DPRA3 => i_FIFO_addrRd(3), + WCLK => Clk, + WE => i_FIFO_DoPush, + SPO => NLW_i_FIFO_Mram_RAM3_SPO_UNCONNECTED, + DPO => NlwRenamedSig_OI_FIFO_DO(2) + ); + i_FIFO_Mram_RAM2 : RAM16X1D + port map ( + A0 => i_FIFO_addrWr(0), + A1 => i_FIFO_addrWr(1), + A2 => i_FIFO_addrWr(2), + A3 => i_FIFO_addrWr(3), + D => DI(1), + DPRA0 => i_FIFO_addrRd(0), + DPRA1 => i_FIFO_addrRd(1), + DPRA2 => i_FIFO_addrRd(2), + DPRA3 => i_FIFO_addrRd(3), + WCLK => Clk, + WE => i_FIFO_DoPush, + SPO => NLW_i_FIFO_Mram_RAM2_SPO_UNCONNECTED, + DPO => NlwRenamedSig_OI_FIFO_DO(1) + ); + i_FIFO_Mram_RAM1 : RAM16X1D + port map ( + A0 => i_FIFO_addrWr(0), + A1 => i_FIFO_addrWr(1), + A2 => i_FIFO_addrWr(2), + A3 => i_FIFO_addrWr(3), + D => DI(0), + DPRA0 => i_FIFO_addrRd(0), + DPRA1 => i_FIFO_addrRd(1), + DPRA2 => i_FIFO_addrRd(2), + DPRA3 => i_FIFO_addrRd(3), + WCLK => Clk, + WE => i_FIFO_DoPush, + SPO => NLW_i_FIFO_Mram_RAM1_SPO_UNCONNECTED, + DPO => NlwRenamedSig_OI_FIFO_DO(0) + ); + i_FIFO_iFull : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => i_FIFO_iFull_and0000, + D => N1, + R => i_FIFO_iFull_or0000, + Q => NlwRenamedSig_OI_i_FIFO_iFull + ); + i_FIFO_iEmpty : FDRE + generic map( + INIT => '1' + ) + port map ( + C => Clk, + CE => i_FIFO_iEmpty_and0000, + D => N1, + R => i_FIFO_iEmpty_or0000, + Q => NlwRenamedSig_OI_i_FIFO_iEmpty + ); + Mcount_cntBits_xor_1_11 : LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => cntBits(1), + I1 => cntBits(0), + O => Result(1) + ); + Mcount_cntBits_xor_2_11 : LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => cntBits(2), + I1 => cntBits(1), + I2 => cntBits(0), + O => Result(2) + ); + Mcount_cntBits_xor_3_11 : LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => cntBits(3), + I1 => cntBits(1), + I2 => cntBits(0), + I3 => cntBits(2), + O => Result(3) + ); + RdNotWr_and00001 : LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => Go, + O => RdNotWr_and0000 + ); + Mcount_cntBytes_xor_1_11 : LUT4 + generic map( + INIT => X"EB41" + ) + port map ( + I0 => RdNotWr_and0000, + I1 => cntBytes(0), + I2 => cntBytes(1), + I3 => ReadCnt(1), + O => Mcount_cntBytes1 + ); + NACK_and00007 : LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => state_FSM_FFd3_239, + I1 => cntSCL(6), + I2 => SDAin, + I3 => cntSCL(1), + O => NACK_and00007_95 + ); + sregOut_mux0000_0_1 : LUT4 + generic map( + INIT => X"FE54" + ) + port map ( + I0 => RdNotWr_and0000, + I1 => NlwRenamedSig_OI_FIFO_DO(0), + I2 => N01, + I3 => Address(0), + O => sregOut_mux0000(0) + ); + SCLout_mux00008 : LUT4 + generic map( + INIT => X"FFBF" + ) + port map ( + I0 => state_FSM_FFd2_235, + I1 => cntSCL(2), + I2 => cntSCL(0), + I3 => cntSCL(7), + O => SCLout_mux00008_122 + ); + SCLout_mux000017 : LUT2 + generic map( + INIT => X"7" + ) + port map ( + I0 => cntSCL(4), + I1 => cntSCL(3), + O => SCLout_mux000017_117 + ); + SCLout_mux000021 : LUT4 + generic map( + INIT => X"FFFB" + ) + port map ( + I0 => cntSCL(1), + I1 => cntSCL(6), + I2 => cntSCL(5), + I3 => SCLout_mux000017_117, + O => SCLout_mux000021_118 + ); + SCLout_mux000061 : LUT4 + generic map( + INIT => X"C040" + ) + port map ( + I0 => state_FSM_FFd4_241, + I1 => cntSCL(0), + I2 => cntSCL(1), + I3 => state_FSM_FFd2_235, + O => SCLout_mux000061_119 + ); + sregIn_and00001 : LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => cntSCL(0), + I1 => state_FSM_FFd1_233, + I2 => N111, + I3 => cntSCL(5), + O => sregIn_and0000 + ); + SDAout_mux0003426 : LUT2 + generic map( + INIT => X"8" + ) + port map ( + I0 => N113, + I1 => SDAout_mux0003412_135, + O => N14 + ); + state_FSM_FFd4_In1 : LUT4 + generic map( + INIT => X"8F88" + ) + port map ( + I0 => Go, + I1 => state_FSM_FFd5_243, + I2 => sclEnd, + I3 => state_FSM_FFd4_241, + O => state_FSM_FFd4_In + ); + state_FSM_FFd2_In2 : LUT3 + generic map( + INIT => X"EA" + ) + port map ( + I0 => state_FSM_FFd1_233, + I1 => RdNotWr_96, + I2 => state_FSM_FFd3_239, + O => state_FSM_FFd2_In2_237 + ); + state_FSM_FFd2_In12 : LUT3 + generic map( + INIT => X"08" + ) + port map ( + I0 => NlwRenamedSig_OI_i_FIFO_iEmpty, + I1 => state_FSM_FFd3_239, + I2 => RdNotWr_96, + O => state_FSM_FFd2_In12_236 + ); + state_FSM_FFd2_In26 : LUT4 + generic map( + INIT => X"2232" + ) + port map ( + I0 => state_FSM_FFd2_In12_236, + I1 => N01, + I2 => state_FSM_FFd2_In2_237, + I3 => N12, + O => state_FSM_FFd2_In26_238 + ); + SDAout_mux00038 : LUT4 + generic map( + INIT => X"0080" + ) + port map ( + I0 => N114, + I1 => cntSCL(0), + I2 => state_FSM_FFd2_235, + I3 => cntSCL(5), + O => SDAout_mux00038_139 + ); + SDAout_mux000316 : LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => cntBytes(0), + I1 => cntBytes(1), + O => SDAout_mux000316_130 + ); + SDAout_mux000325 : LUT4 + generic map( + INIT => X"FF10" + ) + port map ( + I0 => cntBytes(3), + I1 => cntBytes(2), + I2 => SDAout_mux000316_130, + I3 => N01, + O => SDAout_mux000325_133 + ); + SDAout_mux0003431 : LUT4 + generic map( + INIT => X"F888" + ) + port map ( + I0 => state_FSM_FFd1_233, + I1 => SDAout_mux000325_133, + I2 => state_FSM_FFd3_239, + I3 => SDAout_mux000337_134, + O => SDAout_mux0003431_137 + ); + SDAout_mux000393 : LUT4 + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => cntSCL(0), + I1 => cntSCL(6), + I2 => cntSCL(7), + I3 => SDAout_mux000388_140, + O => SDAout_mux000393_141 + ); + SDAout_mux0003112 : LUT4 + generic map( + INIT => X"F7FF" + ) + port map ( + I0 => cntSCL(2), + I1 => cntSCL(5), + I2 => SDAout_mux0003107_126, + I3 => cntSCL(3), + O => SDAout_mux0003112_127 + ); + SDAout_mux0003139 : LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => cntSCL(4), + I1 => cntSCL(1), + O => SDAout_mux0003139_128 + ); + SDAout_mux0003180 : LUT4 + generic map( + INIT => X"FFD8" + ) + port map ( + I0 => state_FSM_FFd4_241, + I1 => SDAout_mux0003112_127, + I2 => SDAout_mux0003157_129, + I3 => SDAout_mux000393_141, + O => SDAout_mux0003180_131 + ); + i_FIFO_Result_1_11 : LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => i_FIFO_addrWr(1), + I1 => i_FIFO_addrWr(0), + O => i_FIFO_Result_1_1_168 + ); + i_FIFO_Result_1_1 : LUT2 + generic map( + INIT => X"6" + ) + port map ( + I0 => i_FIFO_addrRd(1), + I1 => i_FIFO_addrRd(0), + O => i_FIFO_Result(1) + ); + cntBytes_not0001_SW0 : LUT4 + generic map( + INIT => X"F7FF" + ) + port map ( + I0 => cntBits(2), + I1 => cntBits(1), + I2 => cntBits(3), + I3 => cntBits(0), + O => N55 + ); + cntBytes_not0001 : LUT4 + generic map( + INIT => X"F2F0" + ) + port map ( + I0 => state_FSM_FFd1_233, + I1 => N55, + I2 => RdNotWr_and0000, + I3 => sclEnd, + O => cntBytes_not0001_151 + ); + state_FSM_FFd3_In : LUT4 + generic map( + INIT => X"FA8A" + ) + port map ( + I0 => state_FSM_FFd3_239, + I1 => N57, + I2 => sclEnd, + I3 => state_FSM_FFd4_241, + O => state_FSM_FFd3_In_240 + ); + state_FSM_FFd1_In_SW0 : LUT4 + generic map( + INIT => X"A888" + ) + port map ( + I0 => N1111, + I1 => state_FSM_FFd1_233, + I2 => RdNotWr_96, + I3 => state_FSM_FFd3_239, + O => N59 + ); + state_FSM_FFd1_In : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => sclEnd, + I1 => N01, + I2 => N59, + I3 => state_FSM_FFd1_233, + O => state_FSM_FFd1_In_234 + ); + cntSCL_or00001 : LUT2 + generic map( + INIT => X"E" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => sclEnd, + O => cntSCL_or0000 + ); + cntBits_or00001 : LUT3 + generic map( + INIT => X"BA" + ) + port map ( + I0 => state_FSM_FFd4_241, + I1 => N01, + I2 => sclEnd, + O => cntBits_or0000 + ); + sregOut_not000111 : LUT4 + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => cntBits(3), + I1 => cntBits(2), + I2 => cntBits(1), + I3 => cntBits(0), + O => N01 + ); + sregOut_not0001 : LUT4 + generic map( + INIT => X"FEAE" + ) + port map ( + I0 => RdNotWr_and0000, + I1 => N61, + I2 => sclEnd, + I3 => N62, + O => sregOut_not0001_232 + ); + i_FIFO_iFull_and000076 : LUT3 + generic map( + INIT => X"90" + ) + port map ( + I0 => i_FIFO_addrRd(3), + I1 => i_FIFO_Result_3_1, + I2 => i_FIFO_iFull_and000071_189, + O => i_FIFO_iFull_and000076_190 + ); + i_FIFO_iFull_and000096 : LUT3 + generic map( + INIT => X"80" + ) + port map ( + I0 => i_FIFO_iFull_and000048_188, + I1 => i_FIFO_iFull_and000076_190, + I2 => i_FIFO_DoPush, + O => i_FIFO_iFull_and0000 + ); + i_FIFO_DoPop : LUT4 + generic map( + INIT => X"3237" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => N116, + I2 => RdNotWr_96, + I3 => N64, + O => i_FIFO_DoPop_161 + ); + i_FIFO_DoPush40 : LUT4 + generic map( + INIT => X"5444" + ) + port map ( + I0 => NlwRenamedSig_OI_i_FIFO_iFull, + I1 => i_FIFO_DoPush0_163, + I2 => i_FIFO_DoPush13_164, + I3 => sclEnd, + O => i_FIFO_DoPush + ); + SCLout : FDS + generic map( + INIT => '1' + ) + port map ( + C => Clk, + D => SCLout_mux000072, + S => SCLout_mux000063_120, + Q => SCLout_116 + ); + SCLout_mux0000721 : LUT3 + generic map( + INIT => X"A8" + ) + port map ( + I0 => SCLout_116, + I1 => SCLout_mux00008_122, + I2 => SCLout_mux000021_118, + O => SCLout_mux000072 + ); + SDAout : FDS + generic map( + INIT => '1' + ) + port map ( + C => Clk, + D => SDAout_mux0003204, + S => SDAout_mux00038_139, + Q => SDAout_125 + ); + state_FSM_FFd5 : FDRS + generic map( + INIT => '0' + ) + port map ( + C => Clk, + D => state_FSM_FFd5_In1_244, + R => Reset, + S => state_FSM_FFd6_245, + Q => state_FSM_FFd5_243 + ); + state_FSM_FFd2 : FDRE + generic map( + INIT => '0' + ) + port map ( + C => Clk, + CE => sclEnd, + D => state_FSM_FFd2_In26_238, + R => Reset, + Q => state_FSM_FFd2_235 + ); + Mcount_cntSCL_cy_1_rt : LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => cntSCL(1), + O => Mcount_cntSCL_cy_1_rt_43 + ); + Mcount_cntSCL_cy_2_rt : LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => cntSCL(2), + O => Mcount_cntSCL_cy_2_rt_45 + ); + Mcount_cntSCL_cy_3_rt : LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => cntSCL(3), + O => Mcount_cntSCL_cy_3_rt_47 + ); + Mcount_cntSCL_cy_4_rt : LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => cntSCL(4), + O => Mcount_cntSCL_cy_4_rt_49 + ); + Mcount_cntSCL_cy_5_rt : LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => cntSCL(5), + O => Mcount_cntSCL_cy_5_rt_51 + ); + Mcount_cntSCL_cy_6_rt : LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => cntSCL(6), + O => Mcount_cntSCL_cy_6_rt_53 + ); + Mcount_cntSCL_xor_7_rt : LUT1 + generic map( + INIT => X"2" + ) + port map ( + I0 => cntSCL(7), + O => Mcount_cntSCL_xor_7_rt_55 + ); + i_FIFO_DoPop_SW2 : LUT2 + generic map( + INIT => X"1" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => RdNotWr_96, + O => N69 + ); + i_FIFO_iFull_or00001 : LUT4 + generic map( + INIT => X"ABFB" + ) + port map ( + I0 => Reset, + I1 => N65, + I2 => N69, + I3 => N118, + O => i_FIFO_iFull_or0000 + ); + SDAout_mux000332_SW0 : LUT2 + generic map( + INIT => X"B" + ) + port map ( + I0 => cntSCL(0), + I1 => cntSCL(5), + O => N71 + ); + sclEnd_cmp_eq00001 : LUT4 + generic map( + INIT => X"0020" + ) + port map ( + I0 => cntSCL(6), + I1 => cntSCL(1), + I2 => N115, + I3 => N71, + O => sclEnd + ); + SDAout_mux00032041 : LUT4 + generic map( + INIT => X"ECA0" + ) + port map ( + I0 => SDAout_125, + I1 => SDAout_mux000358_138, + I2 => SDAout_mux0003180_131, + I3 => SDAout_mux0003431_137, + O => SDAout_mux0003204 + ); + i_FIFO_DoPush13 : LUT4 + generic map( + INIT => X"0040" + ) + port map ( + I0 => cntBits(3), + I1 => cntBits(2), + I2 => cntBits(1), + I3 => N73, + O => i_FIFO_DoPush13_164 + ); + sclEnd_cmp_eq00001_SW0 : LUT4 + generic map( + INIT => X"FFBF" + ) + port map ( + I0 => cntSCL(1), + I1 => cntSCL(6), + I2 => state_FSM_FFd3_239, + I3 => NlwRenamedSig_OI_i_FIFO_iEmpty, + O => N75 + ); + i_FIFO_iFull_and000071 : LUT4 + generic map( + INIT => X"2148" + ) + port map ( + I0 => i_FIFO_addrWr(1), + I1 => i_FIFO_addrWr(0), + I2 => i_FIFO_addrRd(1), + I3 => i_FIFO_addrRd(0), + O => i_FIFO_iFull_and000071_189 + ); + i_FIFO_Result_3_2 : LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => i_FIFO_addrRd(3), + I1 => i_FIFO_addrRd(2), + I2 => i_FIFO_addrRd(1), + I3 => i_FIFO_addrRd(0), + O => i_FIFO_Result(3) + ); + i_FIFO_Result_3_11 : LUT4 + generic map( + INIT => X"6AAA" + ) + port map ( + I0 => i_FIFO_addrWr(3), + I1 => i_FIFO_addrWr(2), + I2 => i_FIFO_addrWr(1), + I3 => i_FIFO_addrWr(0), + O => i_FIFO_Result_3_1 + ); + i_FIFO_iEmpty_and000058 : LUT4 + generic map( + INIT => X"69C3" + ) + port map ( + I0 => i_FIFO_addrRd(1), + I1 => i_FIFO_addrRd(2), + I2 => i_FIFO_addrWr(2), + I3 => i_FIFO_addrRd(0), + O => i_FIFO_iEmpty_and000058_183 + ); + sregOut_not0001_SW0 : LUT4 + generic map( + INIT => X"8000" + ) + port map ( + I0 => N112, + I1 => SDAout_mux0003425_136, + I2 => state_FSM_FFd3_239, + I3 => N01, + O => N61 + ); + i_FIFO_iEmpty_and000067 : LUT3 + generic map( + INIT => X"69" + ) + port map ( + I0 => i_FIFO_addrRd(1), + I1 => i_FIFO_addrRd(0), + I2 => i_FIFO_addrWr(1), + O => i_FIFO_iEmpty_and000067_184 + ); + i_FIFO_DoPush40_SW0 : LUT3 + generic map( + INIT => X"AE" + ) + port map ( + I0 => Reset, + I1 => N117, + I2 => NlwRenamedSig_OI_i_FIFO_iFull, + O => N79 + ); + i_FIFO_DoPush40_SW1 : LUT2 + generic map( + INIT => X"D" + ) + port map ( + I0 => NlwRenamedSig_OI_i_FIFO_iFull, + I1 => Reset, + O => N80 + ); + i_FIFO_iEmpty_or00001 : LUT4 + generic map( + INIT => X"B8F0" + ) + port map ( + I0 => N80, + I1 => i_FIFO_DoPush13_164, + I2 => N79, + I3 => sclEnd, + O => i_FIFO_iEmpty_or0000 + ); + SDAout_mux0003157_SW0 : LUT4 + generic map( + INIT => X"FF01" + ) + port map ( + I0 => state_FSM_FFd3_239, + I1 => state_FSM_FFd1_233, + I2 => state_FSM_FFd2_235, + I3 => cntSCL(2), + O => N82 + ); + i_FIFO_iEmpty_and0000102 : LUT4 + generic map( + INIT => X"028A" + ) + port map ( + I0 => N77, + I1 => N64, + I2 => N84, + I3 => N85, + O => i_FIFO_iEmpty_and0000 + ); + i_FIFO_iFull_and000048 : LUT4 + generic map( + INIT => X"69C3" + ) + port map ( + I0 => i_FIFO_addrWr(1), + I1 => i_FIFO_addrRd(2), + I2 => i_FIFO_addrWr(2), + I3 => i_FIFO_addrWr(0), + O => i_FIFO_iFull_and000048_188 + ); + NACK_and000020_SW0 : LUT2 + generic map( + INIT => X"D" + ) + port map ( + I0 => cntSCL(0), + I1 => cntSCL(5), + O => N87 + ); + NACK_and000022 : LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => N01, + I1 => N87, + I2 => NACK_and00007_95, + I3 => N15, + O => NACK_and0000 + ); + i_FIFO_DoPop_SW3 : MUXF5 + port map ( + I0 => N1, + I1 => N90, + S => i_FIFO_iEmpty_and000058_183, + O => N84 + ); + i_FIFO_DoPop_SW3_G : LUT4 + generic map( + INIT => X"A8FF" + ) + port map ( + I0 => N65, + I1 => RdNotWr_96, + I2 => state_FSM_FFd5_243, + I3 => i_FIFO_iEmpty_and000067_184, + O => N90 + ); + i_FIFO_DoPop_SW4 : MUXF5 + port map ( + I0 => N1, + I1 => N92, + S => i_FIFO_iEmpty_and000058_183, + O => N85 + ); + i_FIFO_DoPop_SW4_G : LUT4 + generic map( + INIT => X"F1FF" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => N65, + I3 => i_FIFO_iEmpty_and000067_184, + O => N92 + ); + i_FIFO_Result_2_11 : LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => i_FIFO_addrWr(2), + I1 => i_FIFO_addrWr(1), + I2 => i_FIFO_addrWr(0), + O => i_FIFO_Result_2_1_170 + ); + i_FIFO_Result_2_1 : LUT3 + generic map( + INIT => X"6A" + ) + port map ( + I0 => i_FIFO_addrRd(2), + I1 => i_FIFO_addrRd(1), + I2 => i_FIFO_addrRd(0), + O => i_FIFO_Result(2) + ); + SCLout_mux000063 : LUT4 + generic map( + INIT => X"1000" + ) + port map ( + I0 => cntSCL(6), + I1 => cntSCL(5), + I2 => N15, + I3 => SCLout_mux000061_119, + O => SCLout_mux000063_120 + ); + state_FSM_FFd5_In1 : LUT4 + generic map( + INIT => X"8F88" + ) + port map ( + I0 => sclEnd, + I1 => state_FSM_FFd2_235, + I2 => Go, + I3 => state_FSM_FFd5_243, + O => state_FSM_FFd5_In1_244 + ); + Mcount_cntBytes_xor_0_11 : LUT4 + generic map( + INIT => X"B313" + ) + port map ( + I0 => Go, + I1 => cntBytes(0), + I2 => state_FSM_FFd5_243, + I3 => ReadCnt(0), + O => Mcount_cntBytes + ); + DI_7_1 : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => sregIn(7), + I3 => FIFO_DI(7), + O => DI(7) + ); + DI_6_1 : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => sregIn(6), + I3 => FIFO_DI(6), + O => DI(6) + ); + DI_5_1 : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => sregIn(5), + I3 => FIFO_DI(5), + O => DI(5) + ); + DI_4_1 : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => sregIn(4), + I3 => FIFO_DI(4), + O => DI(4) + ); + DI_3_1 : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => sregIn(3), + I3 => FIFO_DI(3), + O => DI(3) + ); + DI_2_1 : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => sregIn(2), + I3 => FIFO_DI(2), + O => DI(2) + ); + DI_1_1 : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => sregIn(1), + I3 => FIFO_DI(1), + O => DI(1) + ); + DI_0_1 : LUT4 + generic map( + INIT => X"FD20" + ) + port map ( + I0 => RdNotWr_96, + I1 => state_FSM_FFd5_243, + I2 => sregIn(0), + I3 => FIFO_DI(0), + O => DI(0) + ); + Mcount_cntBytes_xor_2_1_SW1 : LUT3 + generic map( + INIT => X"C9" + ) + port map ( + I0 => cntBytes(0), + I1 => cntBytes(2), + I2 => cntBytes(1), + O => N107 + ); + Mcount_cntBytes_xor_2_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => Go, + I1 => N107, + I2 => state_FSM_FFd5_243, + I3 => ReadCnt(2), + O => Mcount_cntBytes2 + ); + Mcount_cntBytes_xor_3_1_SW1 : LUT4 + generic map( + INIT => X"AAA9" + ) + port map ( + I0 => cntBytes(3), + I1 => cntBytes(0), + I2 => cntBytes(1), + I3 => cntBytes(2), + O => N109 + ); + Mcount_cntBytes_xor_3_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => Go, + I1 => N109, + I2 => state_FSM_FFd5_243, + I3 => ReadCnt(3), + O => Mcount_cntBytes3 + ); + Mcount_cntSCL_lut_0_INV_0 : INV + port map ( + I => cntSCL(0), + O => Mcount_cntSCL_lut(0) + ); + state_FSM_Out71_INV_0 : INV + port map ( + I => state_FSM_FFd5_243, + O => Busy + ); + i_FIFO_Mcount_addrWr_xor_0_11_INV_0 : INV + port map ( + I => i_FIFO_addrWr(0), + O => i_FIFO_Result_0_1 + ); + i_FIFO_Mcount_addrRd_xor_0_11_INV_0 : INV + port map ( + I => i_FIFO_addrRd(0), + O => i_FIFO_Result(0) + ); + Mcount_cntBits_xor_0_11_INV_0 : INV + port map ( + I => cntBits(0), + O => Result(0) + ); + sregOut_mux0000_7_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => sregOut(6), + I2 => Go, + I3 => Address(7), + O => sregOut_mux0000_7_1_230 + ); + sregOut_mux0000_7_2 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => NlwRenamedSig_OI_FIFO_DO(7), + I2 => Go, + I3 => Address(7), + O => sregOut_mux0000_7_2_231 + ); + sregOut_mux0000_7_f5 : MUXF5 + port map ( + I0 => sregOut_mux0000_7_2_231, + I1 => sregOut_mux0000_7_1_230, + S => N01, + O => sregOut_mux0000(7) + ); + sregOut_mux0000_6_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => sregOut(5), + I2 => Go, + I3 => Address(6), + O => sregOut_mux0000_6_1_227 + ); + sregOut_mux0000_6_2 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => NlwRenamedSig_OI_FIFO_DO(6), + I2 => Go, + I3 => Address(6), + O => sregOut_mux0000_6_2_228 + ); + sregOut_mux0000_6_f5 : MUXF5 + port map ( + I0 => sregOut_mux0000_6_2_228, + I1 => sregOut_mux0000_6_1_227, + S => N01, + O => sregOut_mux0000(6) + ); + sregOut_mux0000_5_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => sregOut(4), + I2 => Go, + I3 => Address(5), + O => sregOut_mux0000_5_1_224 + ); + sregOut_mux0000_5_2 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => NlwRenamedSig_OI_FIFO_DO(5), + I2 => Go, + I3 => Address(5), + O => sregOut_mux0000_5_2_225 + ); + sregOut_mux0000_5_f5 : MUXF5 + port map ( + I0 => sregOut_mux0000_5_2_225, + I1 => sregOut_mux0000_5_1_224, + S => N01, + O => sregOut_mux0000(5) + ); + sregOut_mux0000_4_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => sregOut(3), + I2 => Go, + I3 => Address(4), + O => sregOut_mux0000_4_1_221 + ); + sregOut_mux0000_4_2 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => NlwRenamedSig_OI_FIFO_DO(4), + I2 => Go, + I3 => Address(4), + O => sregOut_mux0000_4_2_222 + ); + sregOut_mux0000_4_f5 : MUXF5 + port map ( + I0 => sregOut_mux0000_4_2_222, + I1 => sregOut_mux0000_4_1_221, + S => N01, + O => sregOut_mux0000(4) + ); + sregOut_mux0000_3_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => sregOut(2), + I2 => Go, + I3 => Address(3), + O => sregOut_mux0000_3_1_218 + ); + sregOut_mux0000_3_2 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => NlwRenamedSig_OI_FIFO_DO(3), + I2 => Go, + I3 => Address(3), + O => sregOut_mux0000_3_2_219 + ); + sregOut_mux0000_3_f5 : MUXF5 + port map ( + I0 => sregOut_mux0000_3_2_219, + I1 => sregOut_mux0000_3_1_218, + S => N01, + O => sregOut_mux0000(3) + ); + sregOut_mux0000_2_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => sregOut(1), + I2 => Go, + I3 => Address(2), + O => sregOut_mux0000_2_1_215 + ); + sregOut_mux0000_2_2 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => NlwRenamedSig_OI_FIFO_DO(2), + I2 => Go, + I3 => Address(2), + O => sregOut_mux0000_2_2_216 + ); + sregOut_mux0000_2_f5 : MUXF5 + port map ( + I0 => sregOut_mux0000_2_2_216, + I1 => sregOut_mux0000_2_1_215, + S => N01, + O => sregOut_mux0000(2) + ); + sregOut_mux0000_1_1 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => sregOut(0), + I2 => Go, + I3 => Address(1), + O => sregOut_mux0000_1_1_212 + ); + sregOut_mux0000_1_2 : LUT4 + generic map( + INIT => X"EC4C" + ) + port map ( + I0 => state_FSM_FFd5_243, + I1 => NlwRenamedSig_OI_FIFO_DO(1), + I2 => Go, + I3 => Address(1), + O => sregOut_mux0000_1_2_213 + ); + sregOut_mux0000_1_f5 : MUXF5 + port map ( + I0 => sregOut_mux0000_1_2_213, + I1 => sregOut_mux0000_1_1_212, + S => N01, + O => sregOut_mux0000(1) + ); + Mcount_cntBytes_xor_3_111 : LUT4_D + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => cntBytes(2), + I1 => cntBytes(3), + I2 => cntBytes(0), + I3 => cntBytes(1), + LO => N1111, + O => N12 + ); + SDAout_mux0003412 : LUT4_D + generic map( + INIT => X"0001" + ) + port map ( + I0 => cntSCL(2), + I1 => cntSCL(4), + I2 => cntSCL(6), + I3 => cntSCL(5), + LO => N112, + O => SDAout_mux0003412_135 + ); + SDAout_mux0003425 : LUT4_D + generic map( + INIT => X"0001" + ) + port map ( + I0 => cntSCL(7), + I1 => cntSCL(3), + I2 => cntSCL(0), + I3 => cntSCL(1), + LO => N113, + O => SDAout_mux0003425_136 + ); + SDAout_mux000337 : LUT2_L + generic map( + INIT => X"B" + ) + port map ( + I0 => sregOut(7), + I1 => N01, + LO => SDAout_mux000337_134 + ); + SDAout_mux000388 : LUT2_L + generic map( + INIT => X"8" + ) + port map ( + I0 => cntSCL(5), + I1 => state_FSM_FFd2_235, + LO => SDAout_mux000388_140 + ); + SDAout_mux0003107 : LUT2_L + generic map( + INIT => X"7" + ) + port map ( + I0 => cntSCL(4), + I1 => cntSCL(1), + LO => SDAout_mux0003107_126 + ); + state_FSM_FFd3_In_SW0 : LUT3_L + generic map( + INIT => X"F1" + ) + port map ( + I0 => RdNotWr_96, + I1 => NlwRenamedSig_OI_i_FIFO_iEmpty, + I2 => N01, + LO => N57 + ); + sregOut_not0001_SW1 : LUT4_L + generic map( + INIT => X"C404" + ) + port map ( + I0 => NlwRenamedSig_OI_i_FIFO_iEmpty, + I1 => state_FSM_FFd3_239, + I2 => N01, + I3 => N14, + LO => N62 + ); + SDAout_mux000332 : LUT3_D + generic map( + INIT => X"08" + ) + port map ( + I0 => N15, + I1 => cntSCL(6), + I2 => cntSCL(1), + LO => N114, + O => N111 + ); + NACK_and000011 : LUT4_D + generic map( + INIT => X"4000" + ) + port map ( + I0 => cntSCL(7), + I1 => cntSCL(3), + I2 => cntSCL(2), + I3 => cntSCL(4), + LO => N115, + O => N15 + ); + i_FIFO_DoPop_SW1 : LUT2_D + generic map( + INIT => X"D" + ) + port map ( + I0 => FIFO_Pop, + I1 => NlwRenamedSig_OI_i_FIFO_iEmpty, + LO => N116, + O => N65 + ); + i_FIFO_DoPush13_SW0 : LUT4_L + generic map( + INIT => X"FF7F" + ) + port map ( + I0 => cntBits(0), + I1 => state_FSM_FFd1_233, + I2 => RdNotWr_96, + I3 => state_FSM_FFd5_243, + LO => N73 + ); + SDAout_mux000358 : LUT4_L + generic map( + INIT => X"1000" + ) + port map ( + I0 => state_FSM_FFd4_241, + I1 => state_FSM_FFd2_235, + I2 => SDAout_mux0003412_135, + I3 => SDAout_mux0003425_136, + LO => SDAout_mux000358_138 + ); + i_FIFO_DoPush0 : LUT3_D + generic map( + INIT => X"C4" + ) + port map ( + I0 => RdNotWr_96, + I1 => FIFO_Push, + I2 => state_FSM_FFd5_243, + LO => N117, + O => i_FIFO_DoPush0_163 + ); + i_FIFO_DoPop_SW0 : LUT4_D + generic map( + INIT => X"FFFD" + ) + port map ( + I0 => N15, + I1 => N71, + I2 => N75, + I3 => N01, + LO => N118, + O => N64 + ); + SDAout_mux0003157 : LUT4_L + generic map( + INIT => X"FFFE" + ) + port map ( + I0 => SDAout_mux0003139_128, + I1 => cntSCL(5), + I2 => cntSCL(3), + I3 => N82, + LO => SDAout_mux0003157_129 + ); + i_FIFO_iEmpty_and0000102_SW0 : LUT4_L + generic map( + INIT => X"0990" + ) + port map ( + I0 => i_FIFO_Result(3), + I1 => i_FIFO_addrWr(3), + I2 => i_FIFO_addrRd(0), + I3 => i_FIFO_addrWr(0), + LO => N77 + ); + +end STRUCTURE; + diff --git a/ucisw2_magnetometr/MagnetoHMC5883LCtrl.jhd b/ucisw2_magnetometr/MagnetoHMC5883LCtrl.jhd new file mode 100644 index 0000000..49f4e38 --- /dev/null +++ b/ucisw2_magnetometr/MagnetoHMC5883LCtrl.jhd @@ -0,0 +1,5 @@ +MODULE MagnetoHMC5883LCtrl + SUBMODULE I2C_Master + INSTANCE I2CCtrl + SUBMODULE Magneto_Drv + INSTANCE MagnetoInterface diff --git a/ucisw2_magnetometr/MagnetoHMC5883LCtrl.sch b/ucisw2_magnetometr/MagnetoHMC5883LCtrl.sch new file mode 100644 index 0000000..794e7e2 --- /dev/null +++ b/ucisw2_magnetometr/MagnetoHMC5883LCtrl.sch @@ -0,0 +1,270 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2015-11-24T14:12:50 + + + + + + + + + + + + + + + + + + + + + + + 2018-4-17T13:58:12 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/ucisw2_magnetometr/MagnetoHMC5883LCtrl.sym b/ucisw2_magnetometr/MagnetoHMC5883LCtrl.sym new file mode 100644 index 0000000..35f0de7 --- /dev/null +++ b/ucisw2_magnetometr/MagnetoHMC5883LCtrl.sym @@ -0,0 +1,50 @@ + + + BLOCK + 2018-5-25T11:43:31 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ucisw2_magnetometr/MagnetoHMC5883LCtrl.vhf b/ucisw2_magnetometr/MagnetoHMC5883LCtrl.vhf new file mode 100644 index 0000000..dfbbba7 --- /dev/null +++ b/ucisw2_magnetometr/MagnetoHMC5883LCtrl.vhf @@ -0,0 +1,135 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 14.7 +-- \ \ Application : sch2hdl +-- / / Filename : MagnetoHMC5883LCtrl.vhf +-- /___/ /\ Timestamp : 05/28/2018 20:43:29 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: sch2hdl -intstyle ise -family spartan6 -flat -suppress -vhdl D:/XilinxPrj/ucisw2_magnetometr/MagnetoHMC5883LCtrl.vhf -w D:/XilinxPrj/ucisw2_magnetometr/MagnetoHMC5883LCtrl.sch +--Design Name: MagnetoHMC5883LCtrl +--Device: spartan6 +--Purpose: +-- This vhdl netlist is translated from an ECS schematic. It can be +-- synthesized and simulated, but it should not be modified. +-- + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity MagnetoHMC5883LCtrl is + port ( Clk : in std_logic; + DRDY : in std_logic; + OutputRate : in std_logic_vector (2 downto 0); + Reset : in std_logic; + DRX : out std_logic_vector (15 downto 0); + DRY : out std_logic_vector (15 downto 0); + DRZ : out std_logic_vector (15 downto 0); + DR_New : out std_logic; + ID : out std_logic_vector (23 downto 0); + NACK : out std_logic; + SCL : inout std_logic; + SDA : inout std_logic); +end MagnetoHMC5883LCtrl; + +architecture BEHAVIORAL of MagnetoHMC5883LCtrl is + signal XLXN_4 : std_logic; + signal XLXN_5 : std_logic; + signal XLXN_6 : std_logic; + signal XLXN_27 : std_logic_vector (7 downto 0); + signal XLXN_28 : std_logic_vector (7 downto 0); + signal XLXN_29 : std_logic_vector (3 downto 0); + signal XLXN_52 : std_logic; + signal XLXN_54 : std_logic; + signal XLXN_55 : std_logic; + signal XLXN_57 : std_logic_vector (7 downto 0); + component I2C_Master + port ( Go : in std_logic; + Address : in std_logic_vector (7 downto 0); + ReadCnt : in std_logic_vector (3 downto 0); + SDA : inout std_logic; + SCL : inout std_logic; + FIFO_Pop : in std_logic; + FIFO_Push : in std_logic; + FIFO_DI : in std_logic_vector (7 downto 0); + FIFO_Empty : out std_logic; + FIFO_Full : out std_logic; + FIFO_DO : out std_logic_vector (7 downto 0); + Reset : in std_logic; + Clk : in std_logic; + Busy : out std_logic; + NACK : out std_logic); + end component; + + component Magneto_Drv + port ( I2C_FIFO_Empty : in std_logic; + I2C_FIFO_Full : in std_logic; + I2C_Busy : in std_logic; + DRDY : in std_logic; + Reset : in std_logic; + Clk : in std_logic; + I2C_FIFO_DO : in std_logic_vector (7 downto 0); + OutputRate : in std_logic_vector (2 downto 0); + I2C_Go : out std_logic; + I2C_FIFO_Push : out std_logic; + I2C_FIFO_Pop : out std_logic; + DR_New : out std_logic; + I2C_FIFO_DI : out std_logic_vector (7 downto 0); + I2C_Addr : out std_logic_vector (7 downto 0); + I2C_ReadCnt : out std_logic_vector (3 downto 0); + ID : out std_logic_vector (23 downto 0); + DRX : out std_logic_vector (15 downto 0); + DRY : out std_logic_vector (15 downto 0); + DRZ : out std_logic_vector (15 downto 0)); + end component; + +begin + I2CCtrl : I2C_Master + port map (Address(7 downto 0)=>XLXN_28(7 downto 0), + Clk=>Clk, + FIFO_DI(7 downto 0)=>XLXN_27(7 downto 0), + FIFO_Pop=>XLXN_6, + FIFO_Push=>XLXN_5, + Go=>XLXN_4, + ReadCnt(3 downto 0)=>XLXN_29(3 downto 0), + Reset=>Reset, + Busy=>XLXN_55, + FIFO_DO(7 downto 0)=>XLXN_57(7 downto 0), + FIFO_Empty=>XLXN_52, + FIFO_Full=>XLXN_54, + NACK=>NACK, + SCL=>SCL, + SDA=>SDA); + + MagnetoInterface : Magneto_Drv + port map (Clk=>Clk, + DRDY=>DRDY, + I2C_Busy=>XLXN_55, + I2C_FIFO_DO(7 downto 0)=>XLXN_57(7 downto 0), + I2C_FIFO_Empty=>XLXN_52, + I2C_FIFO_Full=>XLXN_54, + OutputRate(2 downto 0)=>OutputRate(2 downto 0), + Reset=>Reset, + DRX(15 downto 0)=>DRX(15 downto 0), + DRY(15 downto 0)=>DRY(15 downto 0), + DRZ(15 downto 0)=>DRZ(15 downto 0), + DR_New=>DR_New, + ID(23 downto 0)=>ID(23 downto 0), + I2C_Addr(7 downto 0)=>XLXN_28(7 downto 0), + I2C_FIFO_DI(7 downto 0)=>XLXN_27(7 downto 0), + I2C_FIFO_Pop=>XLXN_6, + I2C_FIFO_Push=>XLXN_5, + I2C_Go=>XLXN_4, + I2C_ReadCnt(3 downto 0)=>XLXN_29(3 downto 0)); + +end BEHAVIORAL; + + diff --git a/ucisw2_magnetometr/Magneto_Drv.spl b/ucisw2_magnetometr/Magneto_Drv.spl new file mode 100644 index 0000000..93535da --- /dev/null +++ b/ucisw2_magnetometr/Magneto_Drv.spl @@ -0,0 +1,19 @@ +[Inputs] +I2C_FIFO_Empty +I2C_FIFO_Full +I2C_Busy +DRDY +Disp_Busy +Start +Reset +Clk +=I2C_FIFO_DO[7:0]= +[Outputs] +I2C_Go +I2C_FIFO_Push +I2C_FIFO_Pop +Disp_Start +=I2C_FIFO_DI[7:0]= +=I2C_Addr[7:0]= +=I2C_ReadCnt[3:0]= +[BiDir] diff --git a/ucisw2_magnetometr/Magneto_Drv.sym b/ucisw2_magnetometr/Magneto_Drv.sym new file mode 100644 index 0000000..adb9f5d --- /dev/null +++ b/ucisw2_magnetometr/Magneto_Drv.sym @@ -0,0 +1,75 @@ + + + BLOCK + 2018-4-17T13:58:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ucisw2_magnetometr/Magneto_Drv.vhd b/ucisw2_magnetometr/Magneto_Drv.vhd new file mode 100644 index 0000000..c66496c --- /dev/null +++ b/ucisw2_magnetometr/Magneto_Drv.vhd @@ -0,0 +1,310 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:16:45 02/27/2018 +-- Design Name: +-- Module Name: Magneto_Drv - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity Magneto_Drv is + Port ( I2C_FIFO_Empty : in STD_LOGIC; + I2C_FIFO_Full : in STD_LOGIC; + I2C_FIFO_DO : in STD_LOGIC_VECTOR (7 downto 0); + I2C_Busy : in STD_LOGIC; + DRDY : in STD_LOGIC; + OutputRate : in STD_LOGIC_VECTOR (2 downto 0); + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + I2C_Go : out STD_LOGIC; + I2C_FIFO_Push : out STD_LOGIC; + I2C_FIFO_Pop : out STD_LOGIC; + I2C_FIFO_DI : out STD_LOGIC_VECTOR (7 downto 0); + I2C_Addr : out STD_LOGIC_VECTOR (7 downto 0); + I2C_ReadCnt : out STD_LOGIC_VECTOR (3 downto 0); + ID : out STD_LOGIC_VECTOR (23 downto 0); + DRX : out STD_LOGIC_VECTOR (15 downto 0); + DRY : out STD_LOGIC_VECTOR (15 downto 0); + DRZ : out STD_LOGIC_VECTOR (15 downto 0); + DR_New : out STD_LOGIC); +end Magneto_Drv; + +architecture Behavioral of Magneto_Drv is + -- Main state machine + type state_type is ( Init, PushAddrID, SendAddrID, BusyAddrID, ReceiveID, BusyID, ReadID, PopID, CheckID, + PushAddrConfigA, PushDataConfigA, SendConfigA, BusyConfigA, PushAddrMode, PushDataMode, + SendMode, BusyMode, MeasureWait, MeasureReceive, MeasureBusy, MeasureRead, MeasurePop, + MeasureCheck, MeasureLoad, MeasureOutput, MeasurePushAddr, MeasureSendAddr, MeasureBusyAddr ); + signal state, next_state : state_type; + + -- DRDY synchronized input + signal DRDY_in : STD_LOGIC; + + -- Input registers + signal ID_reg : STD_LOGIC_VECTOR (23 downto 0); + signal Input : STD_LOGIC_VECTOR (47 downto 0); + + -- Input byte counter + signal bytes : integer range 0 to 5 := 0; + + -- Measure output registers + signal DRX_reg : STD_LOGIC_VECTOR (15 downto 0); + signal DRY_reg : STD_LOGIC_VECTOR (15 downto 0); + signal DRZ_reg : STD_LOGIC_VECTOR (15 downto 0); + +begin + -- DRDY input synchronization to internal clock + sync_process : process(Clk, Reset) + begin + if Reset = '1' then + DRDY_in <= '0'; + elsif rising_edge(Clk) then + DRDY_in <= DRDY; + end if; + end process sync_process; + + -- Main HMC5883L FSM + -- (continuos measurement) + process1 : process(Clk) + begin + if rising_edge(Clk) then + if Reset = '1' then + state <= Init; + else + state <= next_state; + end if; + end if; + end process process1; + + process2 : process(state, I2C_FIFO_Empty, I2C_Busy, DRDY_in) + begin + next_state <= state; -- by default + + case state is + -- Initialization + -- Reading identification register + when Init => + next_state <= PushAddrID; + when PushAddrID => + next_state <= SendAddrID; + when SendAddrID => + next_state <= BusyAddrID; + when BusyAddrID => + if I2C_Busy = '0' then + next_state <= ReceiveID; + end if; + when ReceiveID => + next_state <= BusyID; + when BusyID => + if I2C_Busy = '0' then + next_state <= ReadID; + end if; + when ReadID => + next_state <= PopID; + when PopID => + next_state <= CheckID; + when CheckID => + if I2C_FIFO_Empty = '1' then + next_state <= PushAddrConfigA; + else + next_state <= ReadID; + end if; + -- Setting data rate and mode + when PushAddrConfigA => + next_state <= PushDataConfigA; + when PushDataConfigA => + next_state <= SendConfigA; + when SendConfigA => + next_state <= BusyConfigA; + when BusyConfigA => + if I2C_Busy = '0' then + next_state <= PushAddrMode; + end if; + when PushAddrMode => + next_state <= PushDataMode; + when PushDataMode => + next_state <= SendMode; + when SendMode => + next_state <= BusyMode; + when BusyMode => + if I2C_Busy = '0' then + next_state <= MeasureWait; + end if; + -- Measuring... + when MeasureWait => + if DRDY_in = '0' then + next_state <= MeasureReceive; + end if; + when MeasureReceive => + next_state <= MeasureBusy; + when MeasureBusy => + if I2C_Busy = '0' then + next_state <= MeasureRead; + end if; + -- Reading results... + when MeasureRead => + next_state <= MeasurePop; + when MeasurePop => + next_state <= MeasureCheck; -- + when MeasureCheck => + if I2C_FIFO_Empty = '1' then + next_state <= MeasureLoad; + else + next_state <= MeasureRead; + end if; + when MeasureLoad => + next_state <= MeasureOutput; + when MeasureOutput => + next_state <= MeasurePushAddr; + when MeasurePushAddr => + next_state <= MeasureSendAddr; + when MeasureSendAddr => + next_state <= MeasureBusyAddr; + when MeasureBusyAddr => + if I2C_Busy = '0' then + next_state <= MeasureWait; + end if; + end case; + end process process2; + + id_register : process(Clk, state, next_state) + begin + if rising_edge(Clk) then + if state = ReadID then + case bytes is + when 0 => + ID_reg(23 downto 16) <= I2C_FIFO_DO; + when 1 => + ID_reg(15 downto 8) <= I2C_FIFO_DO; + when 2 => + ID_reg(7 downto 0) <= I2C_FIFO_DO; + when others => + ID_reg <= X"000000"; + end case; + end if; + end if; + end process id_register; + + -- Storing measurements in register + input_register : process(Clk, state, next_state) + begin + if rising_edge(Clk) then + if state = MeasureRead then + case bytes is + when 0 => + Input(47 downto 40) <= I2C_FIFO_DO; + when 1 => + Input(39 downto 32) <= I2C_FIFO_DO; + when 2 => + Input(31 downto 24) <= I2C_FIFO_DO; + when 3 => + Input(23 downto 16) <= I2C_FIFO_DO; + when 4 => + Input(15 downto 8) <= I2C_FIFO_DO; + when 5 => + Input(7 downto 0) <= I2C_FIFO_DO; + end case; + end if; + end if; + end process input_register; + + -- Stored bytes counter + byte_counter : process(Clk) + begin + if rising_edge(Clk) then + if Reset = '1' then + bytes <= 0; + end if; + if state = MeasurePop then + if bytes = 5 then + bytes <= 0; + else + bytes <= bytes + 1; + end if; + end if; + if state = PopID then + if bytes = 2 then + bytes <= 0; + else + bytes <= bytes + 1; + end if; + end if; + end if; + end process byte_counter; + + -- Buffering output in registers + output_sync : process(Clk, state, next_state) + begin + if rising_edge(Clk) then + if state = MeasureLoad then + DRX_reg <= Input(47 downto 32); + DRZ_reg <= Input(31 downto 16); + DRY_reg <= Input(15 downto 0); + end if; + end if; + end process output_sync; + + -- Output signals for FSM + I2C_FIFO_DI <= X"0A" when next_state = PushAddrID or state = PushAddrID else + X"00" when next_state = PushAddrConfigA or state = PushAddrConfigA else + "000" & OutputRate & "00" when next_state = PushDataConfigA or state = PushDataConfigA else + X"02" when next_state = PushAddrMode or state = PushAddrMode else + X"00" when next_state = PushDataMode or state = PushDataMode else + X"03" when next_state = MeasurePushAddr or state = MeasurePushAddr else + X"00"; + + I2C_FIFO_Push <= '1' when state = PushAddrID or state = PushAddrConfigA or state = PushDataConfigA + or state = PushAddrMode or state = PushDataMode or state = MeasurePushAddr else + '0'; + + I2C_Addr <= X"3C" when next_state = SendAddrID or state = SendAddrID or next_state = SendConfigA + or state = SendConfigA or next_state = SendMode or state = SendMode + or next_state = MeasureSendAddr or state = MeasureSendAddr else + X"3D" when next_state = ReceiveID or state = ReceiveID or next_state = MeasureReceive + or state = MeasureReceive else + X"00"; + + I2C_Go <= '1' when state = SendAddrID or state = ReceiveID or state = SendConfigA or state = SendMode + or state = MeasureReceive or state = MeasureSendAddr else + '0'; + + I2C_ReadCnt <= X"3" when next_state = ReceiveID or state = ReceiveID else + X"6" when next_state = MeasureReceive or state = MeasureReceive else + X"0"; + + I2C_FIFO_Pop <= '1' when state = PopID or state = MeasurePop else + '0'; + + DR_New <= '1' when state = MeasureOutput else + '0'; + + -- Output registers + ID <= ID_reg; + DRX <= DRX_reg; + DRY <= DRY_reg; + DRZ <= DRZ_reg; + +end Behavioral; + diff --git a/ucisw2_magnetometr/Magneto_J3.ucf b/ucisw2_magnetometr/Magneto_J3.ucf new file mode 100644 index 0000000..67cf47a --- /dev/null +++ b/ucisw2_magnetometr/Magneto_J3.ucf @@ -0,0 +1,4 @@ +# Magnetometer GY-273 connected to Header J3 (Espier III board) +NET "DRDY" LOC = "P24" | SLEW = SLOW | DRIVE = 6; # shared with PS2_CLK +NET "SDA" LOC = "P57" | SLEW = SLOW | DRIVE = 6; +NET "SCL" LOC = "P58" | SLEW = SLOW | DRIVE = 6; diff --git a/ucisw2_magnetometr/VGACompass.spl b/ucisw2_magnetometr/VGACompass.spl new file mode 100644 index 0000000..ec177e2 --- /dev/null +++ b/ucisw2_magnetometr/VGACompass.spl @@ -0,0 +1,12 @@ +[Inputs] +Reset +Clk +=DRX[15:0]= +=DRY[15:0]= +[Outputs] +H_SYNC +V_SYNC +=V_R[4:0]= +=V_G[5:0]= +=V_B[4:0]= +[BiDir] diff --git a/ucisw2_magnetometr/VGACompass.sym b/ucisw2_magnetometr/VGACompass.sym new file mode 100644 index 0000000..d45c21a --- /dev/null +++ b/ucisw2_magnetometr/VGACompass.sym @@ -0,0 +1,41 @@ + + + BLOCK + 2018-5-28T23:28:4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ucisw2_magnetometr/VGACompass.vhd b/ucisw2_magnetometr/VGACompass.vhd new file mode 100644 index 0000000..354961b --- /dev/null +++ b/ucisw2_magnetometr/VGACompass.vhd @@ -0,0 +1,163 @@ +---------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 13:11:03 05/28/2018 +-- Design Name: +-- Module Name: VGACompass - Behavioral +-- Project Name: +-- Target Devices: +-- Tool versions: +-- Description: +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +use IEEE.NUMERIC_STD.ALL; + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity VGACompass is + Port ( DRX : in STD_LOGIC_VECTOR (15 downto 0); + DRY : in STD_LOGIC_VECTOR (15 downto 0); + Reset : in STD_LOGIC; + Clk : in STD_LOGIC; + V_R : out STD_LOGIC_VECTOR (4 downto 0); + V_G : out STD_LOGIC_VECTOR (5 downto 0); + V_B : out STD_LOGIC_VECTOR (4 downto 0); + H_SYNC : out STD_LOGIC; + V_SYNC : out STD_LOGIC); +end VGACompass; + +architecture Behavioral of VGACompass is + constant h_pulse : integer := 80; -- Horiztonal sync pulse width in pixels + constant h_bp : integer := 160; -- Horiztonal back porch width in pixels + constant h_pixels : integer := 800; -- Horiztonal display width in pixels + constant h_fp : integer := 16; -- Horiztonal front porch width in pixels + constant h_pol : STD_LOGIC := '1'; -- Horizontal sync pulse polarity (1 = positive, 0 = negative) + constant v_pulse : integer := 3; -- Vertical sync pulse width in rows + constant v_bp : integer := 21; -- Vertical back porch width in rows + constant v_pixels : integer := 600; -- Vertical display width in rows + constant v_fp : integer := 1; -- Vertical front porch width in rows + constant v_pol : STD_LOGIC := '1'; -- Vertical sync pulse polarity (1 = positive, 0 = negative) + constant h_period : integer := h_pulse + h_bp + h_pixels + h_fp; -- Total number of pixel clocks in a row + constant v_period : integer := v_pulse + v_bp + v_pixels + v_fp; -- Total number of rows in column + + signal disp_ena : STD_LOGIC; -- Display enable ('1' = display time, '0' = blanking time) + signal column : integer; -- Horizontal pixel coordinate + signal row : integer; -- Vertical pixel coordinate + + signal DataX : signed (15 downto 0) := signed(DRX); + signal DataY : signed (15 downto 0) := signed(DRY); + signal Color : unsigned (15 downto 0) := unsigned((abs(DataX) + abs(DataY)) / 2); + +begin + process(Clk, Reset) + variable h_count : integer range 0 to h_period - 1 := 0; -- Horizontal counter (counts the columns) + variable v_count : integer range 0 to v_period - 1 := 0; -- Vertical counter (counts the rows) + + begin + if rising_edge(Clk) then + if(Reset = '1') then -- Reset asserted + h_count := 0; -- Reset horizontal counter + v_count := 0; -- Reset vertical counter + H_SYNC <= not h_pol; -- Deassert horizontal sync + V_SYNC <= not v_pol; -- Deassert vertical sync + disp_ena <= '0'; -- Disable display + column <= 0; -- Reset column pixel coordinate + row <= 0; -- Reset row pixel coordinate + end if; + + -- Counters + if(h_count < h_period - 1) then + -- Horizontal counter (pixels) + h_count := h_count + 1; + else + h_count := 0; + if(v_count < v_period - 1) then + -- Veritcal counter (rows) + v_count := v_count + 1; + else + v_count := 0; + end if; + end if; + + -- Horizontal sync signal + if(h_count < h_pixels + h_fp or h_count >= h_pixels + h_fp + h_pulse) then + H_SYNC <= not h_pol; -- Deassert horiztonal sync pulse + else + H_SYNC <= h_pol; -- Assert horiztonal sync pulse + end if; + + -- Vertical sync signal + if(v_count < v_pixels + v_fp or v_count >= v_pixels + v_fp + v_pulse) then + V_SYNC <= not v_pol; -- Deassert vertical sync pulse + else + V_SYNC <= v_pol; -- Assert vertical sync pulse + end if; + + -- Set pixel coordinates + if(h_count < h_pixels) then -- Horiztonal display time + column <= h_count; -- Set horiztonal pixel coordinate + end if; + if(v_count < v_pixels) then -- Vertical display time + row <= v_count; -- Set vertical pixel coordinate + end if; + + -- Set display enable signal + if(h_count < h_pixels and v_count < v_pixels) then + -- Display time + disp_ena <= '1'; + else + -- Blanking time + disp_ena <= '0'; + end if; + end if; + end process; + + process(disp_ena, row, column, DataX, DataY, Color) + begin + if(disp_ena = '1') then + -- Display time + if(row > 295 - shift_right(DataX, 3) and column > 395 - shift_right(DataY, 3) and row < 305 - shift_right(DataX, 3) and column < 405 - shift_right(DataY, 3)) then + -- Northern marker (red) + V_R <= (others => '1'); + V_G <= STD_LOGIC_VECTOR(Color(10 downto 5)); + V_B <= (others => '0'); + elsif(row > 295 + shift_right(DataX, 3) and column > 395 + shift_right(DataY, 3) and row < 305 + shift_right(DataX, 3) and column < 405 + shift_right(DataY, 3)) then + -- Southern marker (blue) + V_R <= (others => '0'); + V_G <= STD_LOGIC_VECTOR(Color(10 downto 5)); + V_B <= (others => '1'); + elsif(row = 300 or column = 400) then + -- Axes (yellow) + V_R <= (others => '1'); + V_G <= (others => '1'); + V_B <= (others => '0'); + else + -- Background (black) + V_R <= (others => '0'); + V_G <= (others => '0'); + V_B <= (others => '0'); + end if; + else + -- Blanking time + V_R <= (others => '0'); + V_G <= (others => '0'); + V_B <= (others => '0'); + end if; + end process; +end Behavioral; + diff --git a/ucisw2_magnetometr/magneto_i2c.jhd b/ucisw2_magnetometr/magneto_i2c.jhd new file mode 100644 index 0000000..40f405e --- /dev/null +++ b/ucisw2_magnetometr/magneto_i2c.jhd @@ -0,0 +1,7 @@ +MODULE magneto_i2c + SUBMODULE MagnetoHMC5883LCtrl + INSTANCE MagnetoCtrl + SUBMODULE Display4x7S + INSTANCE ZAxisDisp + SUBMODULE VGACompass + INSTANCE CompassDisp diff --git a/ucisw2_magnetometr/magneto_i2c.sch b/ucisw2_magnetometr/magneto_i2c.sch new file mode 100644 index 0000000..149ff38 --- /dev/null +++ b/ucisw2_magnetometr/magneto_i2c.sch @@ -0,0 +1,268 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + 2018-5-25T11:43:31 + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + 2018-5-25T12:38:38 + + + + + + + + + + + + + + + 2018-5-28T23:28:4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/ucisw2_magnetometr/magneto_i2c.sym b/ucisw2_magnetometr/magneto_i2c.sym new file mode 100644 index 0000000..ef5653d --- /dev/null +++ b/ucisw2_magnetometr/magneto_i2c.sym @@ -0,0 +1,53 @@ + + + BLOCK + 2018-5-26T13:14:4 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ucisw2_magnetometr/magneto_i2c.vhf b/ucisw2_magnetometr/magneto_i2c.vhf new file mode 100644 index 0000000..487e70f --- /dev/null +++ b/ucisw2_magnetometr/magneto_i2c.vhf @@ -0,0 +1,274 @@ +-------------------------------------------------------------------------------- +-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +-------------------------------------------------------------------------------- +-- ____ ____ +-- / /\/ / +-- /___/ \ / Vendor: Xilinx +-- \ \ \/ Version : 14.7 +-- \ \ Application : sch2hdl +-- / / Filename : magneto_i2c.vhf +-- /___/ /\ Timestamp : 05/29/2018 01:34:17 +-- \ \ / \ +-- \___\/\___\ +-- +--Command: sch2hdl -intstyle ise -family spartan6 -flat -suppress -vhdl D:/XilinxPrj/ucisw2_magnetometr/magneto_i2c.vhf -w D:/XilinxPrj/ucisw2_magnetometr/magneto_i2c.sch +--Design Name: magneto_i2c +--Device: spartan6 +--Purpose: +-- This vhdl netlist is translated from an ECS schematic. It can be +-- synthesized and simulated, but it should not be modified. +-- + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity MagnetoHMC5883LCtrl_MUSER_magneto_i2c is + port ( Clk : in std_logic; + DRDY : in std_logic; + OutputRate : in std_logic_vector (2 downto 0); + Reset : in std_logic; + DRX : out std_logic_vector (15 downto 0); + DRY : out std_logic_vector (15 downto 0); + DRZ : out std_logic_vector (15 downto 0); + DR_New : out std_logic; + ID : out std_logic_vector (23 downto 0); + NACK : out std_logic; + SCL : inout std_logic; + SDA : inout std_logic); +end MagnetoHMC5883LCtrl_MUSER_magneto_i2c; + +architecture BEHAVIORAL of MagnetoHMC5883LCtrl_MUSER_magneto_i2c is + signal XLXN_4 : std_logic; + signal XLXN_5 : std_logic; + signal XLXN_6 : std_logic; + signal XLXN_27 : std_logic_vector (7 downto 0); + signal XLXN_28 : std_logic_vector (7 downto 0); + signal XLXN_29 : std_logic_vector (3 downto 0); + signal XLXN_52 : std_logic; + signal XLXN_54 : std_logic; + signal XLXN_55 : std_logic; + signal XLXN_57 : std_logic_vector (7 downto 0); + component I2C_Master + port ( Go : in std_logic; + Address : in std_logic_vector (7 downto 0); + ReadCnt : in std_logic_vector (3 downto 0); + SDA : inout std_logic; + SCL : inout std_logic; + FIFO_Pop : in std_logic; + FIFO_Push : in std_logic; + FIFO_DI : in std_logic_vector (7 downto 0); + FIFO_Empty : out std_logic; + FIFO_Full : out std_logic; + FIFO_DO : out std_logic_vector (7 downto 0); + Reset : in std_logic; + Clk : in std_logic; + Busy : out std_logic; + NACK : out std_logic); + end component; + + component Magneto_Drv + port ( I2C_FIFO_Empty : in std_logic; + I2C_FIFO_Full : in std_logic; + I2C_Busy : in std_logic; + DRDY : in std_logic; + Reset : in std_logic; + Clk : in std_logic; + I2C_FIFO_DO : in std_logic_vector (7 downto 0); + OutputRate : in std_logic_vector (2 downto 0); + I2C_Go : out std_logic; + I2C_FIFO_Push : out std_logic; + I2C_FIFO_Pop : out std_logic; + DR_New : out std_logic; + I2C_FIFO_DI : out std_logic_vector (7 downto 0); + I2C_Addr : out std_logic_vector (7 downto 0); + I2C_ReadCnt : out std_logic_vector (3 downto 0); + ID : out std_logic_vector (23 downto 0); + DRX : out std_logic_vector (15 downto 0); + DRY : out std_logic_vector (15 downto 0); + DRZ : out std_logic_vector (15 downto 0)); + end component; + +begin + I2CCtrl : I2C_Master + port map (Address(7 downto 0)=>XLXN_28(7 downto 0), + Clk=>Clk, + FIFO_DI(7 downto 0)=>XLXN_27(7 downto 0), + FIFO_Pop=>XLXN_6, + FIFO_Push=>XLXN_5, + Go=>XLXN_4, + ReadCnt(3 downto 0)=>XLXN_29(3 downto 0), + Reset=>Reset, + Busy=>XLXN_55, + FIFO_DO(7 downto 0)=>XLXN_57(7 downto 0), + FIFO_Empty=>XLXN_52, + FIFO_Full=>XLXN_54, + NACK=>NACK, + SCL=>SCL, + SDA=>SDA); + + MagnetoInterface : Magneto_Drv + port map (Clk=>Clk, + DRDY=>DRDY, + I2C_Busy=>XLXN_55, + I2C_FIFO_DO(7 downto 0)=>XLXN_57(7 downto 0), + I2C_FIFO_Empty=>XLXN_52, + I2C_FIFO_Full=>XLXN_54, + OutputRate(2 downto 0)=>OutputRate(2 downto 0), + Reset=>Reset, + DRX(15 downto 0)=>DRX(15 downto 0), + DRY(15 downto 0)=>DRY(15 downto 0), + DRZ(15 downto 0)=>DRZ(15 downto 0), + DR_New=>DR_New, + ID(23 downto 0)=>ID(23 downto 0), + I2C_Addr(7 downto 0)=>XLXN_28(7 downto 0), + I2C_FIFO_DI(7 downto 0)=>XLXN_27(7 downto 0), + I2C_FIFO_Pop=>XLXN_6, + I2C_FIFO_Push=>XLXN_5, + I2C_Go=>XLXN_4, + I2C_ReadCnt(3 downto 0)=>XLXN_29(3 downto 0)); + +end BEHAVIORAL; + + + +library ieee; +use ieee.std_logic_1164.ALL; +use ieee.numeric_std.ALL; +library UNISIM; +use UNISIM.Vcomponents.ALL; + +entity magneto_i2c is + port ( CLK : in std_logic; + DRDY : in std_logic; + Rate : in std_logic_vector (2 downto 0); + Reset : in std_logic; + DRLED : out std_logic; + DS : out std_logic_vector (7 downto 0); + DS_EN : out std_logic_vector (3 downto 0); + H_SYNC : out std_logic; + NACK : out std_logic; + V_B : out std_logic_vector (4 downto 0); + V_G : out std_logic_vector (5 downto 0); + V_R : out std_logic_vector (4 downto 0); + V_SYNC : out std_logic; + SCL : inout std_logic; + SDA : inout std_logic); +end magneto_i2c; + +architecture BEHAVIORAL of magneto_i2c is + attribute BOX_TYPE : string ; + signal XLXN_94 : std_logic_vector (2 downto 0); + signal XLXN_110 : std_logic_vector (15 downto 0); + signal XLXN_111 : std_logic_vector (15 downto 0); + signal XLXN_264 : std_logic; + signal XLXN_278 : std_logic_vector (15 downto 0); + signal ZAxisDisp_Blank_openSignal : std_logic_vector (3 downto 0); + signal ZAxisDisp_DP_openSignal : std_logic_vector (3 downto 0); + component VGACompass + port ( Reset : in std_logic; + Clk : in std_logic; + DRX : in std_logic_vector (15 downto 0); + DRY : in std_logic_vector (15 downto 0); + H_SYNC : out std_logic; + V_SYNC : out std_logic; + V_R : out std_logic_vector (4 downto 0); + V_G : out std_logic_vector (5 downto 0); + V_B : out std_logic_vector (4 downto 0)); + end component; + + component MagnetoHMC5883LCtrl_MUSER_magneto_i2c + port ( OutputRate : in std_logic_vector (2 downto 0); + Clk : in std_logic; + Reset : in std_logic; + DRDY : in std_logic; + DR_New : out std_logic; + ID : out std_logic_vector (23 downto 0); + DRX : out std_logic_vector (15 downto 0); + DRY : out std_logic_vector (15 downto 0); + DRZ : out std_logic_vector (15 downto 0); + NACK : out std_logic; + SDA : inout std_logic; + SCL : inout std_logic); + end component; + + component INV + port ( I : in std_logic; + O : out std_logic); + end component; + attribute BOX_TYPE of INV : component is "BLACK_BOX"; + + component BUF + port ( I : in std_logic; + O : out std_logic); + end component; + attribute BOX_TYPE of BUF : component is "BLACK_BOX"; + + component Display4x7S + port ( Clk : in std_logic; + DI : in std_logic_vector (15 downto 0); + DP : in std_logic_vector (3 downto 0); + Blank : in std_logic_vector (3 downto 0); + DS_EN : out std_logic_vector (3 downto 0); + DS : out std_logic_vector (7 downto 0)); + end component; + +begin + CompassDisp : VGACompass + port map (Clk=>CLK, + DRX(15 downto 0)=>XLXN_110(15 downto 0), + DRY(15 downto 0)=>XLXN_111(15 downto 0), + Reset=>XLXN_264, + H_SYNC=>H_SYNC, + V_B(4 downto 0)=>V_B(4 downto 0), + V_G(5 downto 0)=>V_G(5 downto 0), + V_R(4 downto 0)=>V_R(4 downto 0), + V_SYNC=>V_SYNC); + + MagnetoCtrl : MagnetoHMC5883LCtrl_MUSER_magneto_i2c + port map (Clk=>CLK, + DRDY=>DRDY, + OutputRate(2 downto 0)=>XLXN_94(2 downto 0), + Reset=>XLXN_264, + DRX(15 downto 0)=>XLXN_110(15 downto 0), + DRY(15 downto 0)=>XLXN_111(15 downto 0), + DRZ(15 downto 0)=>XLXN_278(15 downto 0), + DR_New=>open, + ID=>open, + NACK=>NACK, + SCL=>SCL, + SDA=>SDA); + + XLXI_5 : INV + port map (I=>Reset, + O=>XLXN_264); + + XLXI_19 : BUF + port map (I=>DRDY, + O=>DRLED); + + XLXI_20_0 : INV + port map (I=>Rate(0), + O=>XLXN_94(0)); + + XLXI_20_1 : INV + port map (I=>Rate(1), + O=>XLXN_94(1)); + + XLXI_20_2 : INV + port map (I=>Rate(2), + O=>XLXN_94(2)); + + ZAxisDisp : Display4x7S + port map (Blank(3 downto 0)=>ZAxisDisp_Blank_openSignal(3 downto 0), + Clk=>CLK, + DI(15 downto 0)=>XLXN_278(15 downto 0), + DP(3 downto 0)=>ZAxisDisp_DP_openSignal(3 downto 0), + DS(7 downto 0)=>DS(7 downto 0), + DS_EN(3 downto 0)=>DS_EN(3 downto 0)); + +end BEHAVIORAL; + + diff --git a/ucisw2_magnetometr/magneto_impact.ipf b/ucisw2_magnetometr/magneto_impact.ipf new file mode 100644 index 0000000..cd82bbf Binary files /dev/null and b/ucisw2_magnetometr/magneto_impact.ipf differ diff --git a/ucisw2_magnetometr/sch2HdlBatchFile b/ucisw2_magnetometr/sch2HdlBatchFile new file mode 100644 index 0000000..7e97b99 --- /dev/null +++ b/ucisw2_magnetometr/sch2HdlBatchFile @@ -0,0 +1 @@ +sch2hdl,-intstyle,ise,-family,spartan6,-flat,-suppress,-vhdl,D:/XilinxPrj/ucisw2_magnetometr/magneto_i2c.vhf,-w,D:/XilinxPrj/ucisw2_magnetometr/magneto_i2c.sch diff --git a/ucisw2_magnetometr/ucisw2_magnetometr.xise b/ucisw2_magnetometr/ucisw2_magnetometr.xise new file mode 100644 index 0000000..97ff9e1 --- /dev/null +++ b/ucisw2_magnetometr/ucisw2_magnetometr.xise @@ -0,0 +1,389 @@ + + + +
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