120 rindas
3.0 KiB
VHDL
120 rindas
3.0 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 21:30:49 01/03/2018
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-- Design Name:
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-- Module Name: Display4x7S - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Display4x7S is
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Port ( DI : in STD_LOGIC_VECTOR (15 downto 0);
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DP : in STD_LOGIC_VECTOR (3 downto 0);
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Blank : in STD_LOGIC_VECTOR (3 downto 0);
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Clk : in STD_LOGIC;
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DS_EN : out STD_LOGIC_VECTOR (3 downto 0);
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DS : out STD_LOGIC_VECTOR (7 downto 0));
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end Display4x7S;
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architecture Behavioral of Display4x7S is
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type state_type is (A, B, C, D);
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signal state, next_state : state_type;
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signal cycles : integer range 0 to 10000 := 0;
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signal Bits : STD_LOGIC_VECTOR (3 downto 0);
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signal Digit : STD_LOGIC_VECTOR (6 downto 0);
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signal Point : STD_LOGIC;
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begin
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process1 : process(Clk)
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begin
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if rising_edge(Clk) then
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-- Clock frequency divider
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-- 48 MHz -> 4800 Hz
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-- (1200 Hz digit refresh rate)
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if cycles = 10000 then
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state <= next_state;
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cycles <= 0;
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else
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cycles <= cycles + 1;
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end if;
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end if;
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end process process1;
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process2 : process(state)
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begin
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next_state <= state; -- by default
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case state is
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when A =>
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next_state <= B;
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when B =>
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next_state <= C;
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when C =>
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next_state <= D;
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when D =>
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next_state <= A;
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end case;
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end process process2;
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Bits <= DI(3 downto 0) when state = A else
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DI(7 downto 4) when state = B else
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DI(11 downto 8) when state = C else
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DI(15 downto 12) when state = D else
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"0000";
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Point <= DP(0) when state = A else
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DP(1) when state = B else
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DP(2) when state = C else
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DP(3) when state = D else
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'0';
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with Bits select
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Digit <= "0111111" when "0000",
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"0000110" when "0001",
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"1011011" when "0010",
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"1001111" when "0011",
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"1100110" when "0100",
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"1101101" when "0101",
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"1111101" when "0110",
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"0000111" when "0111",
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"1111111" when "1000",
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"1101111" when "1001",
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"1011111" when "1010",
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"1111100" when "1011",
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"0111001" when "1100",
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"1011110" when "1101",
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"1111001" when "1110",
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"1110001" when "1111",
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"0000000" when others;
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DS_EN <= "1110" when state = A and Blank(0) = '0' else
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"1101" when state = B and Blank(1) = '0' else
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"1011" when state = C and Blank(2) = '0' else
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"0111" when state = D and Blank(3) = '0' else
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"1111";
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DS <= Point & Digit;
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end Behavioral;
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