136 рядки
5.4 KiB
VHDL
136 рядки
5.4 KiB
VHDL
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-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
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--------------------------------------------------------------------------------
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-- ____ ____
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-- / /\/ /
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-- /___/ \ / Vendor: Xilinx
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-- \ \ \/ Version : 14.7
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-- \ \ Application : sch2hdl
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-- / / Filename : MagnetoHMC5883LCtrl.vhf
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-- /___/ /\ Timestamp : 05/28/2018 20:43:29
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-- \ \ / \
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-- \___\/\___\
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--
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--Command: sch2hdl -intstyle ise -family spartan6 -flat -suppress -vhdl D:/XilinxPrj/ucisw2_magnetometr/MagnetoHMC5883LCtrl.vhf -w D:/XilinxPrj/ucisw2_magnetometr/MagnetoHMC5883LCtrl.sch
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--Design Name: MagnetoHMC5883LCtrl
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--Device: spartan6
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--Purpose:
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-- This vhdl netlist is translated from an ECS schematic. It can be
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-- synthesized and simulated, but it should not be modified.
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--
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library ieee;
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use ieee.std_logic_1164.ALL;
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use ieee.numeric_std.ALL;
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library UNISIM;
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use UNISIM.Vcomponents.ALL;
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entity MagnetoHMC5883LCtrl is
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port ( Clk : in std_logic;
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DRDY : in std_logic;
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OutputRate : in std_logic_vector (2 downto 0);
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Reset : in std_logic;
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DRX : out std_logic_vector (15 downto 0);
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DRY : out std_logic_vector (15 downto 0);
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DRZ : out std_logic_vector (15 downto 0);
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DR_New : out std_logic;
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ID : out std_logic_vector (23 downto 0);
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NACK : out std_logic;
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SCL : inout std_logic;
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SDA : inout std_logic);
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end MagnetoHMC5883LCtrl;
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architecture BEHAVIORAL of MagnetoHMC5883LCtrl is
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signal XLXN_4 : std_logic;
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signal XLXN_5 : std_logic;
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signal XLXN_6 : std_logic;
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signal XLXN_27 : std_logic_vector (7 downto 0);
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signal XLXN_28 : std_logic_vector (7 downto 0);
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signal XLXN_29 : std_logic_vector (3 downto 0);
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signal XLXN_52 : std_logic;
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signal XLXN_54 : std_logic;
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signal XLXN_55 : std_logic;
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signal XLXN_57 : std_logic_vector (7 downto 0);
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component I2C_Master
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port ( Go : in std_logic;
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Address : in std_logic_vector (7 downto 0);
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ReadCnt : in std_logic_vector (3 downto 0);
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SDA : inout std_logic;
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SCL : inout std_logic;
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FIFO_Pop : in std_logic;
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FIFO_Push : in std_logic;
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FIFO_DI : in std_logic_vector (7 downto 0);
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FIFO_Empty : out std_logic;
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FIFO_Full : out std_logic;
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FIFO_DO : out std_logic_vector (7 downto 0);
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Reset : in std_logic;
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Clk : in std_logic;
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Busy : out std_logic;
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NACK : out std_logic);
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end component;
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component Magneto_Drv
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port ( I2C_FIFO_Empty : in std_logic;
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I2C_FIFO_Full : in std_logic;
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I2C_Busy : in std_logic;
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DRDY : in std_logic;
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Reset : in std_logic;
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Clk : in std_logic;
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I2C_FIFO_DO : in std_logic_vector (7 downto 0);
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OutputRate : in std_logic_vector (2 downto 0);
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I2C_Go : out std_logic;
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I2C_FIFO_Push : out std_logic;
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I2C_FIFO_Pop : out std_logic;
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DR_New : out std_logic;
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I2C_FIFO_DI : out std_logic_vector (7 downto 0);
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I2C_Addr : out std_logic_vector (7 downto 0);
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I2C_ReadCnt : out std_logic_vector (3 downto 0);
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ID : out std_logic_vector (23 downto 0);
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DRX : out std_logic_vector (15 downto 0);
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DRY : out std_logic_vector (15 downto 0);
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DRZ : out std_logic_vector (15 downto 0));
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end component;
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begin
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I2CCtrl : I2C_Master
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port map (Address(7 downto 0)=>XLXN_28(7 downto 0),
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Clk=>Clk,
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FIFO_DI(7 downto 0)=>XLXN_27(7 downto 0),
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FIFO_Pop=>XLXN_6,
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FIFO_Push=>XLXN_5,
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Go=>XLXN_4,
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ReadCnt(3 downto 0)=>XLXN_29(3 downto 0),
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Reset=>Reset,
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Busy=>XLXN_55,
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FIFO_DO(7 downto 0)=>XLXN_57(7 downto 0),
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FIFO_Empty=>XLXN_52,
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FIFO_Full=>XLXN_54,
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NACK=>NACK,
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SCL=>SCL,
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SDA=>SDA);
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MagnetoInterface : Magneto_Drv
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port map (Clk=>Clk,
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DRDY=>DRDY,
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I2C_Busy=>XLXN_55,
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I2C_FIFO_DO(7 downto 0)=>XLXN_57(7 downto 0),
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I2C_FIFO_Empty=>XLXN_52,
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I2C_FIFO_Full=>XLXN_54,
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OutputRate(2 downto 0)=>OutputRate(2 downto 0),
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Reset=>Reset,
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DRX(15 downto 0)=>DRX(15 downto 0),
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DRY(15 downto 0)=>DRY(15 downto 0),
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DRZ(15 downto 0)=>DRZ(15 downto 0),
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DR_New=>DR_New,
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ID(23 downto 0)=>ID(23 downto 0),
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I2C_Addr(7 downto 0)=>XLXN_28(7 downto 0),
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I2C_FIFO_DI(7 downto 0)=>XLXN_27(7 downto 0),
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I2C_FIFO_Pop=>XLXN_6,
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I2C_FIFO_Push=>XLXN_5,
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I2C_Go=>XLXN_4,
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I2C_ReadCnt(3 downto 0)=>XLXN_29(3 downto 0));
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end BEHAVIORAL;
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