164 行
5.6 KiB
VHDL
164 行
5.6 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 13:11:03 05/28/2018
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-- Design Name:
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-- Module Name: VGACompass - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity VGACompass is
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Port ( DRX : in STD_LOGIC_VECTOR (15 downto 0);
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DRY : in STD_LOGIC_VECTOR (15 downto 0);
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Reset : in STD_LOGIC;
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Clk : in STD_LOGIC;
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V_R : out STD_LOGIC_VECTOR (4 downto 0);
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V_G : out STD_LOGIC_VECTOR (5 downto 0);
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V_B : out STD_LOGIC_VECTOR (4 downto 0);
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H_SYNC : out STD_LOGIC;
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V_SYNC : out STD_LOGIC);
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end VGACompass;
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architecture Behavioral of VGACompass is
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constant h_pulse : integer := 80; -- Horiztonal sync pulse width in pixels
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constant h_bp : integer := 160; -- Horiztonal back porch width in pixels
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constant h_pixels : integer := 800; -- Horiztonal display width in pixels
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constant h_fp : integer := 16; -- Horiztonal front porch width in pixels
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constant h_pol : STD_LOGIC := '1'; -- Horizontal sync pulse polarity (1 = positive, 0 = negative)
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constant v_pulse : integer := 3; -- Vertical sync pulse width in rows
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constant v_bp : integer := 21; -- Vertical back porch width in rows
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constant v_pixels : integer := 600; -- Vertical display width in rows
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constant v_fp : integer := 1; -- Vertical front porch width in rows
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constant v_pol : STD_LOGIC := '1'; -- Vertical sync pulse polarity (1 = positive, 0 = negative)
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constant h_period : integer := h_pulse + h_bp + h_pixels + h_fp; -- Total number of pixel clocks in a row
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constant v_period : integer := v_pulse + v_bp + v_pixels + v_fp; -- Total number of rows in column
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signal disp_ena : STD_LOGIC; -- Display enable ('1' = display time, '0' = blanking time)
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signal column : integer; -- Horizontal pixel coordinate
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signal row : integer; -- Vertical pixel coordinate
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signal DataX : signed (15 downto 0) := signed(DRX);
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signal DataY : signed (15 downto 0) := signed(DRY);
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signal Color : unsigned (15 downto 0) := unsigned((abs(DataX) + abs(DataY)) / 2);
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begin
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process(Clk, Reset)
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variable h_count : integer range 0 to h_period - 1 := 0; -- Horizontal counter (counts the columns)
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variable v_count : integer range 0 to v_period - 1 := 0; -- Vertical counter (counts the rows)
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begin
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if rising_edge(Clk) then
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if(Reset = '1') then -- Reset asserted
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h_count := 0; -- Reset horizontal counter
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v_count := 0; -- Reset vertical counter
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H_SYNC <= not h_pol; -- Deassert horizontal sync
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V_SYNC <= not v_pol; -- Deassert vertical sync
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disp_ena <= '0'; -- Disable display
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column <= 0; -- Reset column pixel coordinate
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row <= 0; -- Reset row pixel coordinate
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end if;
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-- Counters
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if(h_count < h_period - 1) then
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-- Horizontal counter (pixels)
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h_count := h_count + 1;
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else
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h_count := 0;
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if(v_count < v_period - 1) then
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-- Veritcal counter (rows)
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v_count := v_count + 1;
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else
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v_count := 0;
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end if;
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end if;
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-- Horizontal sync signal
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if(h_count < h_pixels + h_fp or h_count >= h_pixels + h_fp + h_pulse) then
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H_SYNC <= not h_pol; -- Deassert horiztonal sync pulse
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else
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H_SYNC <= h_pol; -- Assert horiztonal sync pulse
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end if;
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-- Vertical sync signal
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if(v_count < v_pixels + v_fp or v_count >= v_pixels + v_fp + v_pulse) then
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V_SYNC <= not v_pol; -- Deassert vertical sync pulse
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else
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V_SYNC <= v_pol; -- Assert vertical sync pulse
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end if;
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-- Set pixel coordinates
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if(h_count < h_pixels) then -- Horiztonal display time
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column <= h_count; -- Set horiztonal pixel coordinate
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end if;
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if(v_count < v_pixels) then -- Vertical display time
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row <= v_count; -- Set vertical pixel coordinate
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end if;
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-- Set display enable signal
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if(h_count < h_pixels and v_count < v_pixels) then
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-- Display time
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disp_ena <= '1';
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else
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-- Blanking time
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disp_ena <= '0';
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end if;
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end if;
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end process;
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process(disp_ena, row, column, DataX, DataY, Color)
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begin
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if(disp_ena = '1') then
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-- Display time
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if(row > 295 - shift_right(DataX, 3) and column > 395 - shift_right(DataY, 3) and row < 305 - shift_right(DataX, 3) and column < 405 - shift_right(DataY, 3)) then
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-- Northern marker (red)
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V_R <= (others => '1');
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V_G <= STD_LOGIC_VECTOR(Color(10 downto 5));
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V_B <= (others => '0');
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elsif(row > 295 + shift_right(DataX, 3) and column > 395 + shift_right(DataY, 3) and row < 305 + shift_right(DataX, 3) and column < 405 + shift_right(DataY, 3)) then
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-- Southern marker (blue)
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V_R <= (others => '0');
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V_G <= STD_LOGIC_VECTOR(Color(10 downto 5));
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V_B <= (others => '1');
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elsif(row = 300 or column = 400) then
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-- Axes (yellow)
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V_R <= (others => '1');
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V_G <= (others => '1');
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V_B <= (others => '0');
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else
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-- Background (black)
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V_R <= (others => '0');
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V_G <= (others => '0');
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V_B <= (others => '0');
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end if;
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else
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-- Blanking time
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V_R <= (others => '0');
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V_G <= (others => '0');
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V_B <= (others => '0');
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end if;
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end process;
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end Behavioral;
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