Projekt z kursu Układy cyfrowe i systemy wbudowane 2 na PWr
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  1. --------------------------------------------------------------------------------
  2. -- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
  3. --------------------------------------------------------------------------------
  4. -- ____ ____
  5. -- / /\/ /
  6. -- /___/ \ / Vendor: Xilinx
  7. -- \ \ \/ Version : 14.7
  8. -- \ \ Application : sch2hdl
  9. -- / / Filename : magneto_i2c.vhf
  10. -- /___/ /\ Timestamp : 05/29/2018 01:34:17
  11. -- \ \ / \
  12. -- \___\/\___\
  13. --
  14. --Command: sch2hdl -intstyle ise -family spartan6 -flat -suppress -vhdl D:/XilinxPrj/ucisw2_magnetometr/magneto_i2c.vhf -w D:/XilinxPrj/ucisw2_magnetometr/magneto_i2c.sch
  15. --Design Name: magneto_i2c
  16. --Device: spartan6
  17. --Purpose:
  18. -- This vhdl netlist is translated from an ECS schematic. It can be
  19. -- synthesized and simulated, but it should not be modified.
  20. --
  21. library ieee;
  22. use ieee.std_logic_1164.ALL;
  23. use ieee.numeric_std.ALL;
  24. library UNISIM;
  25. use UNISIM.Vcomponents.ALL;
  26. entity MagnetoHMC5883LCtrl_MUSER_magneto_i2c is
  27. port ( Clk : in std_logic;
  28. DRDY : in std_logic;
  29. OutputRate : in std_logic_vector (2 downto 0);
  30. Reset : in std_logic;
  31. DRX : out std_logic_vector (15 downto 0);
  32. DRY : out std_logic_vector (15 downto 0);
  33. DRZ : out std_logic_vector (15 downto 0);
  34. DR_New : out std_logic;
  35. ID : out std_logic_vector (23 downto 0);
  36. NACK : out std_logic;
  37. SCL : inout std_logic;
  38. SDA : inout std_logic);
  39. end MagnetoHMC5883LCtrl_MUSER_magneto_i2c;
  40. architecture BEHAVIORAL of MagnetoHMC5883LCtrl_MUSER_magneto_i2c is
  41. signal XLXN_4 : std_logic;
  42. signal XLXN_5 : std_logic;
  43. signal XLXN_6 : std_logic;
  44. signal XLXN_27 : std_logic_vector (7 downto 0);
  45. signal XLXN_28 : std_logic_vector (7 downto 0);
  46. signal XLXN_29 : std_logic_vector (3 downto 0);
  47. signal XLXN_52 : std_logic;
  48. signal XLXN_54 : std_logic;
  49. signal XLXN_55 : std_logic;
  50. signal XLXN_57 : std_logic_vector (7 downto 0);
  51. component I2C_Master
  52. port ( Go : in std_logic;
  53. Address : in std_logic_vector (7 downto 0);
  54. ReadCnt : in std_logic_vector (3 downto 0);
  55. SDA : inout std_logic;
  56. SCL : inout std_logic;
  57. FIFO_Pop : in std_logic;
  58. FIFO_Push : in std_logic;
  59. FIFO_DI : in std_logic_vector (7 downto 0);
  60. FIFO_Empty : out std_logic;
  61. FIFO_Full : out std_logic;
  62. FIFO_DO : out std_logic_vector (7 downto 0);
  63. Reset : in std_logic;
  64. Clk : in std_logic;
  65. Busy : out std_logic;
  66. NACK : out std_logic);
  67. end component;
  68. component Magneto_Drv
  69. port ( I2C_FIFO_Empty : in std_logic;
  70. I2C_FIFO_Full : in std_logic;
  71. I2C_Busy : in std_logic;
  72. DRDY : in std_logic;
  73. Reset : in std_logic;
  74. Clk : in std_logic;
  75. I2C_FIFO_DO : in std_logic_vector (7 downto 0);
  76. OutputRate : in std_logic_vector (2 downto 0);
  77. I2C_Go : out std_logic;
  78. I2C_FIFO_Push : out std_logic;
  79. I2C_FIFO_Pop : out std_logic;
  80. DR_New : out std_logic;
  81. I2C_FIFO_DI : out std_logic_vector (7 downto 0);
  82. I2C_Addr : out std_logic_vector (7 downto 0);
  83. I2C_ReadCnt : out std_logic_vector (3 downto 0);
  84. ID : out std_logic_vector (23 downto 0);
  85. DRX : out std_logic_vector (15 downto 0);
  86. DRY : out std_logic_vector (15 downto 0);
  87. DRZ : out std_logic_vector (15 downto 0));
  88. end component;
  89. begin
  90. I2CCtrl : I2C_Master
  91. port map (Address(7 downto 0)=>XLXN_28(7 downto 0),
  92. Clk=>Clk,
  93. FIFO_DI(7 downto 0)=>XLXN_27(7 downto 0),
  94. FIFO_Pop=>XLXN_6,
  95. FIFO_Push=>XLXN_5,
  96. Go=>XLXN_4,
  97. ReadCnt(3 downto 0)=>XLXN_29(3 downto 0),
  98. Reset=>Reset,
  99. Busy=>XLXN_55,
  100. FIFO_DO(7 downto 0)=>XLXN_57(7 downto 0),
  101. FIFO_Empty=>XLXN_52,
  102. FIFO_Full=>XLXN_54,
  103. NACK=>NACK,
  104. SCL=>SCL,
  105. SDA=>SDA);
  106. MagnetoInterface : Magneto_Drv
  107. port map (Clk=>Clk,
  108. DRDY=>DRDY,
  109. I2C_Busy=>XLXN_55,
  110. I2C_FIFO_DO(7 downto 0)=>XLXN_57(7 downto 0),
  111. I2C_FIFO_Empty=>XLXN_52,
  112. I2C_FIFO_Full=>XLXN_54,
  113. OutputRate(2 downto 0)=>OutputRate(2 downto 0),
  114. Reset=>Reset,
  115. DRX(15 downto 0)=>DRX(15 downto 0),
  116. DRY(15 downto 0)=>DRY(15 downto 0),
  117. DRZ(15 downto 0)=>DRZ(15 downto 0),
  118. DR_New=>DR_New,
  119. ID(23 downto 0)=>ID(23 downto 0),
  120. I2C_Addr(7 downto 0)=>XLXN_28(7 downto 0),
  121. I2C_FIFO_DI(7 downto 0)=>XLXN_27(7 downto 0),
  122. I2C_FIFO_Pop=>XLXN_6,
  123. I2C_FIFO_Push=>XLXN_5,
  124. I2C_Go=>XLXN_4,
  125. I2C_ReadCnt(3 downto 0)=>XLXN_29(3 downto 0));
  126. end BEHAVIORAL;
  127. library ieee;
  128. use ieee.std_logic_1164.ALL;
  129. use ieee.numeric_std.ALL;
  130. library UNISIM;
  131. use UNISIM.Vcomponents.ALL;
  132. entity magneto_i2c is
  133. port ( CLK : in std_logic;
  134. DRDY : in std_logic;
  135. Rate : in std_logic_vector (2 downto 0);
  136. Reset : in std_logic;
  137. DRLED : out std_logic;
  138. DS : out std_logic_vector (7 downto 0);
  139. DS_EN : out std_logic_vector (3 downto 0);
  140. H_SYNC : out std_logic;
  141. NACK : out std_logic;
  142. V_B : out std_logic_vector (4 downto 0);
  143. V_G : out std_logic_vector (5 downto 0);
  144. V_R : out std_logic_vector (4 downto 0);
  145. V_SYNC : out std_logic;
  146. SCL : inout std_logic;
  147. SDA : inout std_logic);
  148. end magneto_i2c;
  149. architecture BEHAVIORAL of magneto_i2c is
  150. attribute BOX_TYPE : string ;
  151. signal XLXN_94 : std_logic_vector (2 downto 0);
  152. signal XLXN_110 : std_logic_vector (15 downto 0);
  153. signal XLXN_111 : std_logic_vector (15 downto 0);
  154. signal XLXN_264 : std_logic;
  155. signal XLXN_278 : std_logic_vector (15 downto 0);
  156. signal ZAxisDisp_Blank_openSignal : std_logic_vector (3 downto 0);
  157. signal ZAxisDisp_DP_openSignal : std_logic_vector (3 downto 0);
  158. component VGACompass
  159. port ( Reset : in std_logic;
  160. Clk : in std_logic;
  161. DRX : in std_logic_vector (15 downto 0);
  162. DRY : in std_logic_vector (15 downto 0);
  163. H_SYNC : out std_logic;
  164. V_SYNC : out std_logic;
  165. V_R : out std_logic_vector (4 downto 0);
  166. V_G : out std_logic_vector (5 downto 0);
  167. V_B : out std_logic_vector (4 downto 0));
  168. end component;
  169. component MagnetoHMC5883LCtrl_MUSER_magneto_i2c
  170. port ( OutputRate : in std_logic_vector (2 downto 0);
  171. Clk : in std_logic;
  172. Reset : in std_logic;
  173. DRDY : in std_logic;
  174. DR_New : out std_logic;
  175. ID : out std_logic_vector (23 downto 0);
  176. DRX : out std_logic_vector (15 downto 0);
  177. DRY : out std_logic_vector (15 downto 0);
  178. DRZ : out std_logic_vector (15 downto 0);
  179. NACK : out std_logic;
  180. SDA : inout std_logic;
  181. SCL : inout std_logic);
  182. end component;
  183. component INV
  184. port ( I : in std_logic;
  185. O : out std_logic);
  186. end component;
  187. attribute BOX_TYPE of INV : component is "BLACK_BOX";
  188. component BUF
  189. port ( I : in std_logic;
  190. O : out std_logic);
  191. end component;
  192. attribute BOX_TYPE of BUF : component is "BLACK_BOX";
  193. component Display4x7S
  194. port ( Clk : in std_logic;
  195. DI : in std_logic_vector (15 downto 0);
  196. DP : in std_logic_vector (3 downto 0);
  197. Blank : in std_logic_vector (3 downto 0);
  198. DS_EN : out std_logic_vector (3 downto 0);
  199. DS : out std_logic_vector (7 downto 0));
  200. end component;
  201. begin
  202. CompassDisp : VGACompass
  203. port map (Clk=>CLK,
  204. DRX(15 downto 0)=>XLXN_110(15 downto 0),
  205. DRY(15 downto 0)=>XLXN_111(15 downto 0),
  206. Reset=>XLXN_264,
  207. H_SYNC=>H_SYNC,
  208. V_B(4 downto 0)=>V_B(4 downto 0),
  209. V_G(5 downto 0)=>V_G(5 downto 0),
  210. V_R(4 downto 0)=>V_R(4 downto 0),
  211. V_SYNC=>V_SYNC);
  212. MagnetoCtrl : MagnetoHMC5883LCtrl_MUSER_magneto_i2c
  213. port map (Clk=>CLK,
  214. DRDY=>DRDY,
  215. OutputRate(2 downto 0)=>XLXN_94(2 downto 0),
  216. Reset=>XLXN_264,
  217. DRX(15 downto 0)=>XLXN_110(15 downto 0),
  218. DRY(15 downto 0)=>XLXN_111(15 downto 0),
  219. DRZ(15 downto 0)=>XLXN_278(15 downto 0),
  220. DR_New=>open,
  221. ID=>open,
  222. NACK=>NACK,
  223. SCL=>SCL,
  224. SDA=>SDA);
  225. XLXI_5 : INV
  226. port map (I=>Reset,
  227. O=>XLXN_264);
  228. XLXI_19 : BUF
  229. port map (I=>DRDY,
  230. O=>DRLED);
  231. XLXI_20_0 : INV
  232. port map (I=>Rate(0),
  233. O=>XLXN_94(0));
  234. XLXI_20_1 : INV
  235. port map (I=>Rate(1),
  236. O=>XLXN_94(1));
  237. XLXI_20_2 : INV
  238. port map (I=>Rate(2),
  239. O=>XLXN_94(2));
  240. ZAxisDisp : Display4x7S
  241. port map (Blank(3 downto 0)=>ZAxisDisp_Blank_openSignal(3 downto 0),
  242. Clk=>CLK,
  243. DI(15 downto 0)=>XLXN_278(15 downto 0),
  244. DP(3 downto 0)=>ZAxisDisp_DP_openSignal(3 downto 0),
  245. DS(7 downto 0)=>DS(7 downto 0),
  246. DS_EN(3 downto 0)=>DS_EN(3 downto 0));
  247. end BEHAVIORAL;