Jan Potocki
311 lines
9.2 KiB
VHDL
311 lines
9.2 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 17:16:45 02/27/2018
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-- Design Name:
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-- Module Name: Magneto_Drv - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity Magneto_Drv is
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Port ( I2C_FIFO_Empty : in STD_LOGIC;
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I2C_FIFO_Full : in STD_LOGIC;
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I2C_FIFO_DO : in STD_LOGIC_VECTOR (7 downto 0);
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I2C_Busy : in STD_LOGIC;
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DRDY : in STD_LOGIC;
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OutputRate : in STD_LOGIC_VECTOR (2 downto 0);
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Reset : in STD_LOGIC;
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Clk : in STD_LOGIC;
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I2C_Go : out STD_LOGIC;
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I2C_FIFO_Push : out STD_LOGIC;
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I2C_FIFO_Pop : out STD_LOGIC;
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I2C_FIFO_DI : out STD_LOGIC_VECTOR (7 downto 0);
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I2C_Addr : out STD_LOGIC_VECTOR (7 downto 0);
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I2C_ReadCnt : out STD_LOGIC_VECTOR (3 downto 0);
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ID : out STD_LOGIC_VECTOR (23 downto 0);
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DRX : out STD_LOGIC_VECTOR (15 downto 0);
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DRY : out STD_LOGIC_VECTOR (15 downto 0);
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DRZ : out STD_LOGIC_VECTOR (15 downto 0);
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DR_New : out STD_LOGIC);
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end Magneto_Drv;
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architecture Behavioral of Magneto_Drv is
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-- Main state machine
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type state_type is ( Init, PushAddrID, SendAddrID, BusyAddrID, ReceiveID, BusyID, ReadID, PopID, CheckID,
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PushAddrConfigA, PushDataConfigA, SendConfigA, BusyConfigA, PushAddrMode, PushDataMode,
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SendMode, BusyMode, MeasureWait, MeasureReceive, MeasureBusy, MeasureRead, MeasurePop,
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MeasureCheck, MeasureLoad, MeasureOutput, MeasurePushAddr, MeasureSendAddr, MeasureBusyAddr );
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signal state, next_state : state_type;
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-- DRDY synchronized input
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signal DRDY_in : STD_LOGIC;
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-- Input registers
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signal ID_reg : STD_LOGIC_VECTOR (23 downto 0);
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signal Input : STD_LOGIC_VECTOR (47 downto 0);
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-- Input byte counter
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signal bytes : integer range 0 to 5 := 0;
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-- Measure output registers
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signal DRX_reg : STD_LOGIC_VECTOR (15 downto 0);
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signal DRY_reg : STD_LOGIC_VECTOR (15 downto 0);
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signal DRZ_reg : STD_LOGIC_VECTOR (15 downto 0);
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begin
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-- DRDY input synchronization to internal clock
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sync_process : process(Clk, Reset)
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begin
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if Reset = '1' then
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DRDY_in <= '0';
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elsif rising_edge(Clk) then
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DRDY_in <= DRDY;
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end if;
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end process sync_process;
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-- Main HMC5883L FSM
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-- (continuos measurement)
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process1 : process(Clk)
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begin
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if rising_edge(Clk) then
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if Reset = '1' then
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state <= Init;
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else
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state <= next_state;
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end if;
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end if;
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end process process1;
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process2 : process(state, I2C_FIFO_Empty, I2C_Busy, DRDY_in)
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begin
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next_state <= state; -- by default
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case state is
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-- Initialization
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-- Reading identification register
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when Init =>
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next_state <= PushAddrID;
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when PushAddrID =>
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next_state <= SendAddrID;
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when SendAddrID =>
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next_state <= BusyAddrID;
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when BusyAddrID =>
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if I2C_Busy = '0' then
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next_state <= ReceiveID;
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end if;
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when ReceiveID =>
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next_state <= BusyID;
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when BusyID =>
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if I2C_Busy = '0' then
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next_state <= ReadID;
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end if;
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when ReadID =>
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next_state <= PopID;
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when PopID =>
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next_state <= CheckID;
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when CheckID =>
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if I2C_FIFO_Empty = '1' then
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next_state <= PushAddrConfigA;
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else
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next_state <= ReadID;
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end if;
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-- Setting data rate and mode
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when PushAddrConfigA =>
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next_state <= PushDataConfigA;
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when PushDataConfigA =>
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next_state <= SendConfigA;
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when SendConfigA =>
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next_state <= BusyConfigA;
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when BusyConfigA =>
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if I2C_Busy = '0' then
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next_state <= PushAddrMode;
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end if;
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when PushAddrMode =>
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next_state <= PushDataMode;
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when PushDataMode =>
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next_state <= SendMode;
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when SendMode =>
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next_state <= BusyMode;
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when BusyMode =>
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if I2C_Busy = '0' then
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next_state <= MeasureWait;
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end if;
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-- Measuring...
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when MeasureWait =>
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if DRDY_in = '0' then
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next_state <= MeasureReceive;
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end if;
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when MeasureReceive =>
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next_state <= MeasureBusy;
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when MeasureBusy =>
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if I2C_Busy = '0' then
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next_state <= MeasureRead;
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end if;
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-- Reading results...
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when MeasureRead =>
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next_state <= MeasurePop;
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when MeasurePop =>
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next_state <= MeasureCheck; --
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when MeasureCheck =>
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if I2C_FIFO_Empty = '1' then
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next_state <= MeasureLoad;
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else
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next_state <= MeasureRead;
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end if;
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when MeasureLoad =>
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next_state <= MeasureOutput;
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when MeasureOutput =>
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next_state <= MeasurePushAddr;
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when MeasurePushAddr =>
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next_state <= MeasureSendAddr;
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when MeasureSendAddr =>
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next_state <= MeasureBusyAddr;
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when MeasureBusyAddr =>
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if I2C_Busy = '0' then
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next_state <= MeasureWait;
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end if;
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end case;
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end process process2;
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id_register : process(Clk, state, next_state)
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begin
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if rising_edge(Clk) then
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if state = ReadID then
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case bytes is
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when 0 =>
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ID_reg(23 downto 16) <= I2C_FIFO_DO;
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when 1 =>
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ID_reg(15 downto 8) <= I2C_FIFO_DO;
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when 2 =>
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ID_reg(7 downto 0) <= I2C_FIFO_DO;
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when others =>
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ID_reg <= X"000000";
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end case;
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end if;
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end if;
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end process id_register;
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-- Storing measurements in register
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input_register : process(Clk, state, next_state)
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begin
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if rising_edge(Clk) then
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if state = MeasureRead then
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case bytes is
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when 0 =>
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Input(47 downto 40) <= I2C_FIFO_DO;
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when 1 =>
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Input(39 downto 32) <= I2C_FIFO_DO;
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when 2 =>
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Input(31 downto 24) <= I2C_FIFO_DO;
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when 3 =>
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Input(23 downto 16) <= I2C_FIFO_DO;
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when 4 =>
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Input(15 downto 8) <= I2C_FIFO_DO;
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when 5 =>
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Input(7 downto 0) <= I2C_FIFO_DO;
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end case;
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end if;
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end if;
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end process input_register;
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-- Stored bytes counter
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byte_counter : process(Clk)
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begin
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if rising_edge(Clk) then
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if Reset = '1' then
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bytes <= 0;
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end if;
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if state = MeasurePop then
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if bytes = 5 then
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bytes <= 0;
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else
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bytes <= bytes + 1;
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end if;
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end if;
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if state = PopID then
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if bytes = 2 then
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bytes <= 0;
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else
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bytes <= bytes + 1;
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end if;
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end if;
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end if;
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end process byte_counter;
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-- Buffering output in registers
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output_sync : process(Clk, state, next_state)
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begin
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if rising_edge(Clk) then
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if state = MeasureLoad then
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DRX_reg <= Input(47 downto 32);
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DRZ_reg <= Input(31 downto 16);
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DRY_reg <= Input(15 downto 0);
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end if;
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end if;
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end process output_sync;
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-- Output signals for FSM
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I2C_FIFO_DI <= X"0A" when next_state = PushAddrID or state = PushAddrID else
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X"00" when next_state = PushAddrConfigA or state = PushAddrConfigA else
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"000" & OutputRate & "00" when next_state = PushDataConfigA or state = PushDataConfigA else
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X"02" when next_state = PushAddrMode or state = PushAddrMode else
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X"00" when next_state = PushDataMode or state = PushDataMode else
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X"03" when next_state = MeasurePushAddr or state = MeasurePushAddr else
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X"00";
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I2C_FIFO_Push <= '1' when state = PushAddrID or state = PushAddrConfigA or state = PushDataConfigA
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or state = PushAddrMode or state = PushDataMode or state = MeasurePushAddr else
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'0';
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I2C_Addr <= X"3C" when next_state = SendAddrID or state = SendAddrID or next_state = SendConfigA
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or state = SendConfigA or next_state = SendMode or state = SendMode
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or next_state = MeasureSendAddr or state = MeasureSendAddr else
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X"3D" when next_state = ReceiveID or state = ReceiveID or next_state = MeasureReceive
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or state = MeasureReceive else
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X"00";
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I2C_Go <= '1' when state = SendAddrID or state = ReceiveID or state = SendConfigA or state = SendMode
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or state = MeasureReceive or state = MeasureSendAddr else
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'0';
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I2C_ReadCnt <= X"3" when next_state = ReceiveID or state = ReceiveID else
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X"6" when next_state = MeasureReceive or state = MeasureReceive else
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X"0";
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I2C_FIFO_Pop <= '1' when state = PopID or state = MeasurePop else
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'0';
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DR_New <= '1' when state = MeasureOutput else
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'0';
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-- Output registers
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ID <= ID_reg;
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DRX <= DRX_reg;
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DRY <= DRY_reg;
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DRZ <= DRZ_reg;
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end Behavioral;
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